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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: Automated Device Placement and Routing—Row-based Device Placement

In this blog, I will focus on the automated placement step that is powered by an…

• 3 min read
Automatic Placement , Virtuoso Placer , Auto P&R , Virtuosity , Virtuoso Placement , Custom IC Design

The India Circuit

CDNLive India 2019: And The Best Paper Award Goes To...

What a whirlwind of two months it has been! And it has been totally worth it, with…

• 1 min read
CDNLive India , CDNLive , cadence , Cadence India , UserConference

PCB、IC封装：设计与仿真分析

Ken的博客系列之四 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：IBIS-AMI建模 启用约束驱动设计 通过构建预布局测试平台，填入相关模型，生成结果逼真的仿真结果，这时候正适合启用约束来驱动和控制串行链路的物理布局…

• less than a min read
SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性 , SI分析与建模

Breakfast Bytes

HOT CHIPS: Intel

At HOT CHIPS in August, Intel was everywhere. The two announcements that I'm going…

• 3 min read
Intel , spring hill , deep learning , Vision P6 , accelerator , Tensilica , AI

System, PCB, & Package Design 

BoardSurfers: PCB Design Technique for Designing a Small RF Section in a Digital…

Are you designing a 5G or radar application, or for that matter any application,…

• 3 min read
5G , RF PCB , Allegro PCB Editor

Analog/Custom Design

Spectre Xplored - The New Spectre X Simulator

New Spectre X Simulator enables large-scale simulation for complex analog, RF, and…

• 2 min read
Circuit simulation , simulation performance , ADE , Spectre Tech Tips , Virtuoso Analog Design Environment , Spectre , simulation

Breakfast Bytes

CDNLive China 2019

A couple of weeks ago it was CDNLive China in Shanghai. (To read about how I got…

• 6 min read
CDNLive , cdnlive china

Digital Design

Now Access Online Support Directly from the Tool Interface

As designs become complex and performance targets increase, time shrinks. Designers…

• 1 min read
Digital Implementation forums , Cadence Online Support , Digital Implementation , Innovus

System, PCB, & Package Design 

IC Packagers: Rule Your Package Designs

When it comes to package design, spacing often reigns supreme. The location readout…

• 4 min read
SiP Layout

Breakfast Bytes

Ford: Automotive OEM to Software Manufacturer?

Soon after Marc Andreesen founded the venture capital firm Andreesen-Horowitz (a16z…

• 7 min read
Automotive , ADAS , autonomous vehicles , automobil elektronik kongress , Ford

Breakfast Bytes

HOT CHIPS: Chipletifying Designs

At HOT CHIPS last week, one of the themes that ran through several of the presentations…

• 3 min read
chiplet , hot chips

Breakfast Bytes

Sunday Brunch Video for 25th August 2019

https://youtu.be/RUWt6mOAUUU Made at EBC (camera Sean) Monday: HOT CHIPS 2019 …

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Ken的博客系列之三 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：PCB互连的预布局建模 IBIS-AMI建模 假设我们的PCIExpress Gen 4串行链路，使用初始的PCB走线和过孔模型…

• less than a min read
SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性 , SI分析与建模

Breakfast Bytes

HOT CHIPS: Microsoft Hololens 2

The very last presentation at HOT CHIPS earlier this week was by Elene Terry of Microsoft…

• 3 min read
hololens , microsoft , Tensilica

Verification

Automotive Security in the World of Tomorrow - Part 2 of 2

If you missed the first part of this series, you can find it here . So: what does…

• 2 min read
security , Automotive , Functional Verification , Green Hills Software

Analog/Custom Design

Virtuosity: An Introduction to Modgen

This blog provides an overview of Virtuoso Module Generator, also referred to as…

• 3 min read
EAD , Modgen On Canvas , MODGEN , automation , Automatic Placement , module generation , Module Generator , Layout , Custom IC Design , modgens , Virtuoso Layout Suite , Virtuoso Layout Suite XL

Breakfast Bytes

HOT CHIPS: The Biggest Chip in the World

At HOT CHIPS earlier this week, Cerebras announced the biggest chip in the world…

• 6 min read
artificial intelligence , deep learning , cerebras , wafer scale integration , TSMC , hot chips , AI

Verification

Automotive Security in the World of Tomorrow - Part 1 of 2

Autonomous vehicles are coming. In a statistic from the U.S. Department of Transportation…

• 3 min read
security , Automotive , Functional Verification , Green Hills Software

Analog/Custom Design

SPECTRE 19.1 Release Now Available

The SPECTRE 19.1 production release is now available for download.

• 1 min read
Dynamic Checks , Spectre Fault Analysis , SPECTRE 19.1 , Spectre X Simulator
CDNS - Fix Layout Hompage