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Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Breakfast Bytes

Online Regulations in England and Australia

Everyone in technology, even as far down the value chain as EDA and semiconductors…

• 5 min read
free speech , gdpr , european union

Breakfast Bytes

SEMICON China: 100,000 Visitors

China is hugely important for electronics in general and semiconductor in particular…

• 7 min read
semicon china , semi

Breakfast Bytes

Genus and Innovus: Compus and iSpatial

Yesterday I covered the first part of Chuck Alpert's presentation on the upcoming…

• 5 min read
Genus , CDNLive , Innovus , Synthesis

Whiteboard Wednesdays

Whiteboard Wednesdays - CloudBurst - Fast, Painless, Proven Solution for Hybrid Cloud…

In this week's Whiteboard Wednesdays video, Craig Johnson explains the reasons behind…

• less than a min read
Whiteboard Wednesdays , Cloud-based Design , cloudburst

Breakfast Bytes

Genus and Innovus: Together at Last

Yesterday I wrote about a presentation at CDNLive Silicon Valley Qualcomm: Bring…

• 5 min read
Genus , CDNLive , Synthesis , CDNLive Silicon Valley

定制IC芯片设计

Virtuosity: 运行计划助手的新功能-第一部分

事实证明，Virtuoso ADE Assembler 中的运行计划助手是最流行的功能之一。它提供了在单个会话中创建多个设置变体的功能，每个运行都有自己的设置详细信息…

• less than a min read
Chinese blog , Analog Design Environment , Virtuoso , Run Plan , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

BoardSurfers: Place Replicate to Increase IP Reuse and Decrease Design Time

Once you have successfully designed and optimized an area of your substrate today…

• 4 min read
Place Replicate Module , Allegro PCB Editor

Breakfast Bytes

Qualcomm: Bring Me My Snapdragons

I'm writing this before the Game of Thrones season opener last night. But since last…

• 5 min read
Genus , CDNLive , Qualcomm , Innovus , Synthesis , CDNLive Silicon Valley

Breakfast Bytes

Sunday Brunch Video for 14th April 2019

https://youtu.be/ml397HeOHcc Made at Steve Brown's Tesla in Cadence parking lot…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

如何利用Virtuoso平台高效精确地设计一款射频前端模块电路（一）

作为一名射频前端设计的工程师，大家肯定都有过这样的疑惑：我究竟是做IC设计的，还是做板级电路设计的？如果是前者，为什么我们做仿真不跑corner，不跑蒙特卡罗，甚至连个精确的晶体管模型都没有…

• less than a min read
射频 , Chinese blog , 仿真分析 , 射频前端模块 , 协同仿真 , Virtuoso , 中文

Breakfast Bytes

Brad Brim and the History of Signal Integrity

I sat down with Brad Brim recently. He was retiring from Cadence literally the following…

• 6 min read
system analysis , Signal Integrity , Sigrity , clarity

System, PCB, & Package Design 

Power Plane Loop Inductance Guidance for PDN Designers

Gaining an understanding of power plane loop inductance is important for efficient…

• 1 min read
SI , DesignCon , PDN , Power plane loop inductance , DesignCon 2019 , Signal Integrity , Sigrity , PowerSI

Analog/Custom Design

Virtuoso Video Diary: Creating and Previewing Stimuli

If you've ever tried to add stimuli to your design using the Stimuli form, you'll…

• 3 min read
ADE Explorer , stimuli form , stimuli , Virtuoso Analog Design Environment , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler , Stimuli Assignment form

Breakfast Bytes

Superhuman Photonic Design

I recently came across an article titled Generative Design Could Radically Transform…

• 3 min read
curvycore , Lumerical , silicon photonics , Virtuoso , photonics

Breakfast Bytes

TI's Experience Taping out with Pegasus

At the recent CDNLive Silicon Valley, Kyle Peavy of Texas Instruments (TI) presented…

• 5 min read
CDNLive , pegasus , DRC , design rule check , CDNLive Silicon Valley

Analog/Custom Design

Virtuoso Video Diary: Tune In to the MPT Video Channel

Tune In to the MPT Video Channel to check out a wide range of features easily accessible…

• 1 min read
ICADVM18.1 , video , Layout , Virtuoso , Virtuoso Video Diary , advanced nodes , multi-patterning technology , Custom IC

Whiteboard Wednesdays

Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual…

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun…

• less than a min read
Whiteboard Wednesdays , Quantus , IVMF

Breakfast Bytes

Barefoot in a CloudBurst: Tempus on 2000+ CPUs

Barefoot Networks gave a couple of presentations at the recent CDNLive Silicon Valley…

• 5 min read
CDNLive , barefoot networks , cloudburst , cadence cloud , CDNLive Silicon Valley

Breakfast Bytes

Driving Dangerously

I've written a few times before about the fragility of neural networks, for example…

• 5 min read
Automotive , deep learning , tesla , ADAS , neural networks
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