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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Cloud

Build a Cadence Burst-to-Cloud Hybrid EDA Workflow with NetApp on AWS

The accelerated innovations in semiconductor design have raised customers' expectations…

• 5 min read
cloud bursting , NetApp , FlexCache , EDA , Data Synchronization , Lift and Shift , aws , cadence cloud , hybrid cloud , xcelium

Digital Design

Binge on Chip Design Concepts this Weekend!

In today's semiconductor era, every minute, you always look for the opportunity to…

• 2 min read
Genus , training , YouTube , training bytes , Digital Implementation , Synthesis

Digital Design

Voltus Voice: Breaking Ground with Voltus InsightAI—AI’s Debut in EM-IR Analysis

This blog introduces Voltus InsightAI, an AI-driven in-design solution for early…

• 4 min read
artificial intelligence , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Generative AI , Power Integrity , Voltus InsightAI , Innovus , EMIR

Verification

RISC-V: Democratizing Innovation in CPU Design

RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally…

• 3 min read

Verification

Cadence Memory Models - The Gold Standard

In today’s world, we’ve been seeing an unprecedented rise in the use of “data” with…

• 4 min read
Verification IP , Functional Verification , Cadence VIP portfolio , VIP , memory models

Spotlight Taiwan

一場跨生態系的永續旅程

科技產業越來越關注永續性議題，有些企業在特定永續領域強化，亦有企業著眼在全面性、系統層級的角度來考量永續。 Cadence作為一家在整體科技產業供應鏈扮演關鍵角色的企業…

• less than a min read
digital twin , sustainability , taiwanese blog

System, PCB, & Package Design 

Installation Know-How: Easy Software Updates in OrCAD X and Allegro X on Windows

Like any software application or electronic gadget, software updates are crucial…

• 2 min read
Installation Know-How , cadence , software update , license , Allegro OrCAD Installer , Download Manager , PCB design , OrCAD X , installation , allegro x

Analog/Custom Design

Virtuoso Meets Maxwell: Virtuoso Studio Revolutionizes SiP DRC Verification

Welcome to the fast-paced world of semiconductor design, where every detail counts…

• 5 min read
cross-fabric , SiP , DRC , Virtuoso Meets Maxwell , Package Design in Virtuoso , Virtuoso , Checks , Allegro

Verification

Testing and Training HBM (High Bandwidth Memory) DRAM Using IEEE 1500

HBM is a JEDEC (Joint Electron Device Engineering Council) standard-defined DRAM…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

Computational Fluid Dynamics

Can CFD Replace Roll Decay Tank Testing for Ships

While there is an existing empirical method for estimating roll damping, it has limitations…

• 6 min read
CFD , Roll decay , marine , Fidelity Fine Marine , simulation software

Verification

Serial NAND Flash: New Octal SPI Dual Data Rate Capabilities

Serial NAND Flash NAND Flash has been in a constant battle to prove its competitive…

• 5 min read
Verification IP , Functional Verification , NAND flash controller , serial flash , VIP , octal spi , flash memory , Memory Model , MMAV

カスタムIC／ミックスシグナル

Virtuoso Studio: 私は正しい？ 寄生抽出の観点

By Vinod KheraTranslator: Yasuyuki Iwasa 当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio…

• less than a min read
Virtuoso Studio , EMIR Extraction , japanese blog , SDR , Parasitic extraction

Verification

Riding the AI Wave Using HBM (High Bandwidth Memory)

The ever-increasing innovations in artificial intelligence (AI) are revolutionizing…

• 3 min read
Verification IP , uvm , Functional Verification , Cadence VIP portfolio , System Design and Verification , VIP , Memory Model Portfolio , memory models , verification

System, PCB, & Package Design 

Podcast Episode 2: PCB 3.0: How Will AI Play a Role?

Generative design is an innovative approach that leverages artificial intelligence…

• less than a min read
Artificial Intelligence , PCB design , AI , Allegro

カスタムIC／ミックスシグナル

Doc Assistant A-Z: Cadenceクラウドベースのヘルプビューアを最大限に活用する: Part 1

オフィスのコーヒーステーションは、人々がぶつかり合い、普段はあまり交流のない人々に話す機会を与えるために戦略的に設計されているのではないかと思うことがあります。もしそうなら…

• less than a min read
In-Tool Help , user documentation , in-built help , Cloud-Based Help , japanese blog , Doc Assistant

Spotlight Taiwan

【徵文投稿】CadenceCONNECT Taiwan 2024 大會 - 起跑!

- 創新應用、探索未來 -面對日益複雜的製程發展與應用挑戰，設計不只能為創意實現、更進而形塑未來創新。Cadence立足台灣逾35年，始終為本地客戶、夥伴的最佳助手…

• less than a min read
taiwanese blog , CadenceCONNECT Taiwan

Corporate News

Captivating Advances in Olympic Broadcasting Technology

From the early years of radio transmissions to the modern era of ultra-high-definition…

• 6 min read
EDA tools , Olympics , Broadcasting Technology , 2024 Paris Olympics , technology , chips

Verification

LPDDR5X Opening New Markets for Low-Power DRAMs

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , Low Power DRAMs , Memory , LPDDR Market , LPDDR , VIP , JEDEC , lpddr5 , lpddr5x , verification

System, PCB, & Package Design 

Cadence OrCAD X and Allegro X 23.1 HotFix 003 is Now Available

The HotFix 003 (QIR 1) update for OrCAD X and Allegro X 23.1 release is now available…

• 7 min read
OrCAD X Capture CIS , Cadence Design Systems , padstack editor , Sigrity Aurora , featured , new features , Allegro X PCB Editor , PSpiceA/D , Allegro X Advanced Package Designer , what's new , APD , Cadence Doc Assistant , CDA , PSPICE , hotfix , PCB design , OrCAD X Presto , OrCAD X , 23.1 , Pulse , allegro x , HotFix 003 , Allegro X System Capture
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