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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Life at Cadence

Accelerating the Move to Society 5.0

Our world has gone through many transformations, and technology is accelerating these…

• 3 min read
Industry 4.0 , society 5.0 , intelligent system design

Breakfast Bytes

IEDM Keynote: Ann Kelleher on Future Technology

IEDM 2022 celebrated 75 Years of the Transistor. I wrote about it myself in my post…

• 4 min read
Intel , featured , IEDM , iedm 2022

Computational Fluid Dynamics

Adhering to User Preferences with Entity Selection

It is often a cumbersome task to select the entities that ought to be modified individually…

• 4 min read
CFD , user preferences , Meshing Monday , engineering , simulation software , entity selection , Mesh Generation , Cadence CFD , Fidelity Pointwise

Verification

SD Host Controller for SD Card Verification

SD Host Controller was introduced to transfer data to SD Card from system memory…

• 2 min read
Verification IP , host , Memory , VIP , SD

RF /マイクロ波設計

μWaveRiders:成功するAWR Design Environmentでの設計 - レイアウトと部品ライブラリ

When starting a new design, it's important to take the time to consider design recommendations…

• 1 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Component library , Layout , microwave office , japanese blog , Visual System Simulator(VSS)

Breakfast Bytes

Sunday Brunch Video for 18th December 2022

https://youtu.be/fvfpclonVzo Made at Deer Hollow Farm (camera Carey) Monday: ChatGPT…

• less than a min read
sunday brunch

RF Engineering

μWaveRiders: Setting Up a Successful AWR Design Environment Design - Layout and Component…

When starting a new design, it's important to take the time to consider design recommendations…

• 8 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Component library , Layout , microwave office , Visual System Simulator (VSS)

Digital Design

Training Insights - RTL-to-GDSII Lab: Just One Click to Increase Your Confidence…

Are you struggling to run the RTL2GDSII labs? Want to speed up your learning time…

• 3 min read
Physical verification , ECO , conformal , IMC , Static timing analysis , DFT , Silicon Signoff and Verification , Genus , hold , rail analysis , Tempus , Routing , ASIC flow , LEC , drv , STA , Setup and Hold Analysis , Floorplanning , RTL-to-GDSII , Logic Design , coverage analysis , xrun , setup , logic equivalence checking , digital implementation , GDSII export , Innovus , digital full flow , physical design , Timing analysis , rtl2gds2 , Power Analysis , xcelium , CTS , RTL2GDSII , Synthesis , Placement , Tempus Timing Signoff Solution , IR drop , physical implementation

Breakfast Bytes

Photonics: Riding the Waves

Coming up on January 11th is our annual photonics event. This year it is called CadenceCONNECT…

• 4 min read
Lumerical , silicon photonics , photonics

Analog/Custom Design

Virtuosity: Annotating Scalar Outputs for Single-Point Simulation in Virtuoso Visualization…

Can scalar outputs for single-point simulation be annotated in the graph window of…

• 3 min read
annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

System, PCB, & Package Design 

Ascent: Training Insights: Controlling Design Versions in Allegro System Capture

The Version Control feature in Allegro® System Capture lets you track every modification…

• 4 min read
PCB , System Capture , 17.4 , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Allegro

Life at Cadence

EV Maritime Is Creating Better Boats for a Better World

EV Maritime is a New Zealand-based marine technology business, decarbonizing the…

• 1 min read
CFD , designed with cadence

Breakfast Bytes

RISC-V Summit 2022

The RISC-V Summit took place in December. It was in person and virtual. Clearly,…

• 3 min read
risc-v , risc-v summit , walden international , risc-v foundation , Qualcomm , calista redmond

Life at Cadence

Words and Their Impact on Diversity, Equity, and Inclusion

An employee's perspective about diversity, equity, and inclusion: The Words Matter…

• 4 min read
Insights on Culture , inclusion , Technical Communications , GPTW , my life at cadence , WomenAtCadence , diversity , returnship , wordsmatterinitiative , inclusivelanguage , equity

Breakfast Bytes

CES 2023 Preview: Come and See Us in the Venetian

It's nearly a New Year, and as usual, CES (what used to be called the Consumer Electronics…

• 3 min read
Consumer Electronics Show , tensilica dsp , CES , Tensilica

Analog/Custom Design

Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal…

Do you know you can speed up analog or mixed-signal simulations with digital mixed…

• 9 min read
real number modeling , AMS , AMS Designer , training , DMS , training bytes , Spectre , RNM , AMS simulation , xcelium , Modeling , wreal , Custom IC Design , wreal Model , AMS Verification , vams

Breakfast Bytes

Using Clarity 3D Solver to Analyze 3D Packaging

3D packaging is becoming an increasingly popular solution for protecting and packaging…

• 3 min read
system-in-package , 3dhi , 3DIC , clarity

Digital Design

Knowledge Booster Training Bytes - In-Design Pegasus Signoff Verify Design (SVD)

In-Design Pegasus Signoff Verify Design (SVD) integrates Pegasus Signoff and Pegasus…

• 5 min read
Pegasus Verification System , pegasus , DRC , training bytes , Innovus , signoff , silicon signoff , RAKs , verification

Computational Fluid Dynamics

Last Week at Fidelity CFD

The year 2022 may be coming to an end, but Cadence Fidelity CFD never stops. Here…

• 3 min read
CFD , Pointwise , Computational Fluid Dynamics , adaptation , Mesh Generation
CDNS - Fix Layout Hompage