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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
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Blog - Post List
Latest blogs

Computational Fluid Dynamics

Why Use T-Rex Hybrid Meshing?

As a CFD practitioner, have you experienced difficulty generating meshes in regions…

• 4 min read
CFD , surface meshing , Pointwise , T-Rex meshing , Fidelity CFD , engineering , simulation software , Mesh Generation , hybrid meshing

Verification

USB3 Gen T Tunneling Over USB4

USB Promoter Group recently released USB4 Version 2.0 and this updated specification…

• 2 min read

The India Circuit

Cadence India’s Flagship CSR Initiative, the Cadence Scholarship Program, Recogn…

Cadence India’s flagship Corporate Social Responsibility (CSR) initiative, the Cadence…

• 1 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Academic Network

Announcement of the Availabilty of Verification Education Kit

www.youtube.com/watch Four years ago, I wrote a blog, “ Status of Verification Education…

• 1 min read
Cadence Academic Network , Functional Verification , Education Kits , Protium , Palladium , xcelium , JasperGold , verification

Verification

DDR5 DIMM Design and Verification Considerations

DDR5 is the latest generation of the DDR server memory capable of supporting data…

• 4 min read
Verification IP , ddr5 , DDR5 DIMM , VIP , JEDEC , LRDIMM , DRAM , RDIMM , memory models , PCDDR , verification

PCB設計／ICパッケージ設計

Ascent: Training Insights: Allegro System Captureでデザインバリアント(仕向け設定)を管理する

ボードのアセンブリは、PCB 開発プロセスにおいて最後の重要なステップのひとつです。 パーツを慎重に選択することは、特に、アセンブリ用に最終パーツの情報を送信する前において最も重要です…

• 1 min read
System Capture , Training Insights , Allegro System Capture , japanese blog , variants , ASCENT

Verification

UCIe: Enabling the Chiplet-Based Ecosystem

Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines…

• 2 min read
ucie , Verification IP , chiplets , System Design and Verification , VIP

Verification

Introduction to Embedded DisplayPort (eDP) version 1.5

Embedded DisplayPort 1.5 (eDP 1.5) is an interface standard that is based on the…

• 1 min read
Verification IP , Functional Verification , DisplayPort , VESA , EDP

Computational Fluid Dynamics

Last Week at Fidelity CFD

Happy New Year and welcome to the first post of 2023 when we look back at what's…

• 3 min read
CFD , Marine Engineering , FINE Marine , AIAA SciTech , webinars , Computational Fluid Dynamics , cadencelive , Mesh Generation , Conferences

Data Center

Thésée DataCenter Are Providing Colocation Services Like No Other

Thésée DataCenter is a sovereign, eco-responsible colocation data center, offering…

• 1 min read
futurefacilities , data center , digital twin , designed with cadence , 6sigma

Computational Fluid Dynamics

On-Demand Webinar - End-to-end Design and Modeling of Turbo Compressors for Hydrogen…

Hydrogen fuel is considered one of the most promising means to achieve decarbonization…

• 1 min read
CFD , featured , turbomachinery , webinars , Computational Fluid Dynamics , Cadence Fidelity , fluid dynamics , Fidelity CFD , Turbo , Cadence CFD

System, PCB, & Package Design 

(P)SpiceItUp: Optimizing Parasitic Capacitance in a PCB Design Using PSpice Advanced…

The impact of parasitic capacitance is the primary cause of concern for high-frequency…

• 3 min read
PSpiceA/D , 22.1 , (P)SpiceItUp , PSPICE , optimization , 17.4-2019 , PCB design , PSpice Advanced Analysis , Allegro System Capture , Allegro

PCB設計／ICパッケージ設計

ASCENT: 回路図とPCBレイアウトを同期させる

デザインの開発とメンテナンスを成功させるためには、回路図とPCBレイアウトの変更を追跡し、どのバージョンの回路デザインデータがPCBレイアウトにロードされたかの判断を可能にする…

• less than a min read
System Capture , schematic layout linking , Allegro Pulse , Allegro System Capture , japanese blog , ASCENT , design synchronization

The India Circuit

Manjunath: Taking No Shortcuts to Success

Manjunath's Story Manjunath is a witty young man with a lot of passion and hunger…

• 2 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Analog/Custom Design

Start Your Engines: Mixed-Signal Behavioral Modeling Review and Coaching

AHDL Linter utility checks analog behavioral code for modules and highlights the…

• 5 min read
AMS , ADE Explorer , AMS Designer , mixed signal solution , Mixed-Signal , Virtuoso Analog Design Environment , analog/mixed-signal , mixed-signal solution , AMS Verification , mixed-signal verification , ADE Assembler

Life at Cadence

My Life at Cadence: Thierry Berdah Kraz

For today’s employee spotlight, we are joined by Thierry Berdah Kraz, a director…

• less than a min read
Insights on Culture , Culture , Cadence Culture , my life at cadence , gpw , great place to work , life at cadence , cadence emea

PCB解析／ICパッケージ解析

リジッド-フレックスPCBの折れ曲がり部のEM解析を手間なく実施

リジッド-フレックスPCBを使用するデバイスの機能、安全性、有効性は非常に重要です。特に、高度な医療用インプラントや高精度の重要な軍用機器などに使用されるデバイスおよび類似の規制や分類を持つデバイスでは…

• less than a min read
rigidflex , electromagnetic , japanese blog , Clarity 3D Solver

RF /マイクロ波設計

ナレッジ ブースター トレーニング バイト - Microwave Office でのデータセットの操作

データ セットは、Microwave Office の強力で使いやすい機能です。 データは、グラフや回路図で簡単に交換できます。

• less than a min read
RF Simulation , AWR Design Environment , awr , AWR customization , AWR Microwave Office , microwave office , japanese blog

RF /マイクロ波設計

ナレッジ ブースター トレーニング バイト - Microwave Office における回路図とそのレイアウトの密接な関係

Microwave Office は、III-V 5G チップから基板内の RF システムおよびパッケージ技術まで、あらゆるものを設計する RF およびマイクロ波設計者向けに選ばれたCadenceのツールです…

• less than a min read
RF , RF Simulation , RF designer , AWR customization , RF design , microwave office , japanese blog
CDNS - Fix Layout Hompage