Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Life at Cadence

Formula 1: We Don’t Want Flying Cars - What F1 Teaches Us About Aerodynamics

Formula 1 car design requires extensive analysis of aerodynamics. Computational Fluid…

• 5 min read
CFD , F1 , Computational Fluid Dynamics , Aerodynamics

System, PCB, & Package Design 

BoardSurfers: Managing Design Constraints Efficiently Using Constraint Sets

A constraint is a user-defined property, or a rule, applied to a physical object…

• 4 min read
PCB , 17.4 , BoardSurfers , PCB Editor , Constraint Manager , 17.4-2019 , PCB design , Constraints , Allegro PCB Editor , Constraint Set , Allegro

Breakfast Bytes

Books: Hyperscale and Automotive

I wrote a book! To be more precise, I worked with co-authors to write two books.…

• 3 min read
Automotive , featured , hyperscale , book

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: Cadence Celsius Thermal Solver: FEAとCFDによる完全な熱ソ…

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
CFD , Celsius Thermal Solver , celsius , thermal management , PDN , Power Dissipation , Thermal Basics , 3DIC , IC package design , Computational Fluid Dynamics , PCB design , japanese blog , FEA

System, PCB, & Package Design 

This Month in IDA

IDA activities in August showcased two video interviews with David Maliniak of Microwaves…

• less than a min read
encryption , in-design analysis , optimization , Signal Integrity , electromagnetic , Thermal Analysis , microwave design , multiphysics

Life at Cadence

Analog, RF, and Photonics into One System: The Best Way to Integrate

Modern Chip Architects are balancing more demands than ever as they design whole…

• 4 min read

Breakfast Bytes

HOT CHIPS Day 1: Hot Chiplets

I've said before that HOT CHIPS is one of the best places to absorb the zeitgeist…

• 4 min read
chiplet , 3DIC , 2.5D IC , hot chips , interposer , hotchips2022

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: PCIe 5.0の初期設計サインオフを迅速化させるTopology WorkbenchのPCIe…

System Analysis Knowledge Bytesブログシリーズでは、Cadence® が提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
Sigrity and Systems Analysis , system analysis , PCIe , Signal Integrity , Sigrity , High Speed design , power-aware SI , japanese blog

Computational Fluid Dynamics

Quilting for Easier Meshing!

Fidelity Pointwise includes the concept of meshing regions defined on the CAD level…

• 2 min read
quilting , Meshing Monday , Computational Fluid Dynamics , Fidelity CFD , engineering , simulation software , Meshing

Life at Cadence

Ever-Expanding Applications and Markets Provide Opportunity to Drive Diversity in…

I recently saw a compelling ad on TV by an iconic social media company that served…

• 3 min read
STEM , DEI

Breakfast Bytes

Offtopic: Austria for Canoes and Mask Writing

It's Labor Day on Monday here in the US, a day that traditionally marks the end of…

• 8 min read
semianalysis , offtopic , austria , Olympics

Life at Cadence

Madhu’s Journey to Returnship

Cadence provides diversified opportunities to pursue a career in tech and our Returnship…

• less than a min read
Women at Cadence , LifeAtCadence , returnship

Digital Design

Brain on Fire - AI/ML Art Creation

No matter how you feel about the topic, we're definitely past the turning point in…

FormerMember • 1 min read
Silicon Signoff and Verification , Genus , Tempus , cerebrus , Digital Implementation , Innovus

Verification

Flash Toggle NAND 4.0 in a Nutshell

NAND Flash memory is now a widely accepted non-volatile memory in many application…

• 2 min read
Verification IP , Memory , flash , VIP , verification

Life at Cadence

Formula 1: Hybrid Era & System-Level Power Usage Optimization

Understand how Cadence helps at the system level with power usage optimization in…

• 6 min read
F1 , power

Breakfast Bytes

Space Debris and the Kessler Syndrome

One of the YouTube channels that I am subscribed to is SpaceX. But it's gotten very…

• 6 min read
spacex , space , satellite

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso RF SolutionのAssisted Flowの完成

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• 1 min read
Layout SiP , Viltuoso MultiTech Framework , Enablement GUI , VRF , Virtuoso Meets Maxwell , fully assisted , Virtuoso RF Solution , VMT , Assisted Export , System Design Environment , SiP Layout Option , ICADVM20.1 , japanese blog , Assisted Flows , Assisted Import

カスタムIC／ミックスシグナル

Virtuosity: カスタムIC設計フロー／手法 - 回路物理検証と寄生抽出

カスタム／ミックスドシグナル設計における現在の課題は、高速でシリコン精度の高い手法を持つことです。このブログ・シリーズでは、カスタムICの設計フローと手法の段階についてご紹介します…

• 1 min read
design rule violations , Extraction , Layout versus schematic , Physical Verification System (PVS) , Virtuoso , Quantus Extraction Solution , PVS , japanese blog , Custom IC Design , parasitics

System, PCB, & Package Design 

Quickchat Video Interview: Introducing Cadence Optimality and OnCloud for Systems…

Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently…

• less than a min read
SaaS , featured , in-design analysis , optimization , multiphysics
CDNS - Fix Layout Hompage