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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
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Latest blogs

Breakfast Bytes

CES 2023 Trends

I attended CES 2023 in Las Vegas in the first week of January. You would already…

• 6 min read
CES , ces2023 , health

Computational Fluid Dynamics

Easing the CFD Engineer's Life with Automated Meshing

Mesh generation is where the user’s expertise and ingenuity can influence the convergence…

• 5 min read
CFD , Automated meshing , T-Rex meshing , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Breakfast Bytes

Sunday Brunch Video for 8th January 2023

https://youtu.be/gnS8jvfGL2c Made at Levi's Stadium (camera Gary Bengier) Monday…

• less than a min read
sunday brunch

RF Engineering

Knowledge Booster Training Bytes - Working with Data Sets in Microwave Office

Data sets are a powerful and easy-to-use feature in Microwave Office. Data can be…

• 1 min read
RF Simulation , AWR Design Environment , awr , AWR customization , AWR Microwave Office , microwave office

Breakfast Bytes

CES 2023: AMD, Stellantis, Cadence, and More

It is CES in Las Vegas this week. All things consumer electronics. Cadence's base…

• 6 min read
CES , Tensilica

System, PCB, & Package Design 

DATA Pulse: Publishing to a PLM System Using Allegro Pulse as a Layout Source

To share Allegro® System Capture design data stored in Allegro® Pulse with others…

• 2 min read
PFM template , publish for manufacturing , 22.1 , layout source , Allegro Pulse , Allegro System Capture , Pulse , PLM

Corporate News

Penn Electric Racing Are Revving Things Up with Celsius and AWR

Penn Electric Racing are the University of Pennsylvania’s Formula Electric SAE team…

• 2 min read

Breakfast Bytes

CS + Math

In most domains, a million is a large number. In EDA, a hundred billion is normal…

• 6 min read
heuristics , featured , computational software , EDA , neural networks

Verification

Training Insights – VHDL Language and Application

Cadence has released a new online VHDL training course free for Cadence Customers…

• 2 min read

Computational Fluid Dynamics

On-Demand Webinar: Making the Shipping Sector Greener by Leveraging CFD

CFD tools have become commonplace to optimize vessel design and reduce lifetime fuel…

• less than a min read
CFD , Marine Engineering , shipping , FINE Marine , featured , marine design , naval architecture , marine , Computational Fluid Dynamics , webinar , fluid dynamics , CFD Applications , Cadence CFD , naval

RF Engineering

Knowledge Booster Training Bytes - The Close Connection Between Schematics and Their…

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing…

• 1 min read
RF , RF Simulation , RF designer , AWR customization , RF design , microwave office

Breakfast Bytes

Offtopic: Thanks

Happy New Year! Normally, as you will know if you are a regular reader of Breakfast…

• 8 min read
offtopic , Thanks

Computational Fluid Dynamics

Defining a Good Grid for Solution Accuracy

CFD practitioners must decide on several simulation aspects, such as solution algorithms…

• 5 min read
Mesh quality metrics , Meshing Monday , advection , Computational Fluid Dynamics , Solution Accuracy , engineering , simulation software , Cadence CFD , Meshing , Fidelity Pointwise

Breakfast Bytes

Sunday Brunch Video for 25th December 2022

https://youtu.be/V2368Zo4Tb4 Direct link if it says the video is blocked, Made…

• less than a min read
Breakfast Bytes

カスタムIC／ミックスシグナル

Virtuosity: ViVA XLでのシングル・ポイント・シミュレーションのスカラー出力のアノテーション

私たちは、製品を使いやすくすること、簡単にアクセスできるようにすること、視覚的に魅力的であることがユーザビリティの考え方であると言われている世の中に生きています…

• less than a min read
annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , japanese blog , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

Life at Cadence

Honda Is Replacing Their Manual Meshing Processes with Cadence CFD

When it comes to cars, motorcycles, and power equipment, Honda is a household name…

• 1 min read
CFD , designed with cadence , fidelity , NUMECA , Omnis , Honda

Life at Cadence

LPDDR5X: Why Mobile Memory Matters More than Ever

Since its ratification in the mid-2000s, low-power DDR (LPDDR) has been fundamental…

• 5 min read
featured , lpddr5x , Denali

Breakfast Bytes

Cadence's DDR Portfolio...and LPDDR5X-8533

At the recent CadenceLIVE Europe, Marc Greenberg presented Cadence's portfolio of…

• 5 min read
ddr5 , Memory , featured , DRAM , lpddr5 , DDR

Digital Design

Voltus Voice: Dulce Domum and Happy Holidays!

A recap of the power integrity posts in the Voltus Voice blog series through 2022…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , Power-Efficient Design , hierarchical power integrity analysis , Thermal Integrity , Power Analysis , vector profiling , vectorless
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