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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides…

• 3 min read
Spectre X EMIR , Voltus-Fi-XL , Virtuoso Analog Design Environment , Spectre X distributed simulation , Spectre X Simulator

Breakfast Bytes

CadenceLIVE: Pegasus on AWS, Let Physical Verification Fly

At CadenceLIVE Silicon Valley, Ahmed Elzeftawi of AWS and Dibyendu Goswami of Cadence…

• 4 min read
Physical verification , pegasus , DRC , cloud , aws , cadence cloud

Academic Network

Cadence Academic Network at 59DAC

The Cadence Academic Network was excited to participate in many activities at the…

• 2 min read
DAC , Young Fellows , featured , Cadence Academic Network , CMC Microsystems

System, PCB, & Package Design 

In-Design Analysis in the Cloud with Cadence OnCloud

Last month at CadenceLive Silicon Valley, Cadence introduced a software-as-a-service…

• less than a min read
Power Integrity , in-design analysis , Signal Integrity , electromagnetic , thermal

Breakfast Bytes

ITF USA: Luc Van den hove on Deep Tech

The afternoon of the Monday of SEMICON West is always the Imec Technology Forum …

• 6 min read
itf usa 2022 , imec , itf

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Accelerating Early Stage Design Sign-Off Using PCIe…

This blog talks about how the Cadence®︎ AdvancedSI tools, which are packaged in the…

• 4 min read
Sigrity and Systems Analysis , High Speed Structure Optimization , PCIe , Signal Integrity , High Speed design , power-aware SI

Breakfast Bytes

CadenceLIVE: Do You Know What CMP Is?

I was talking to someone at Cadence recently and I was surprised that he didn't know…

• 4 min read
CMP

System, PCB, & Package Design 

Shift Left: Moving Multiphysics into the Mainstream

As electronic systems have grown incrementally more complex, with more features packed…

• 1 min read
in-design analysis , Electromagnetic analysis , Signal Integrity , Thermal Analysis , microwave design

Breakfast Bytes

Andreas Kuehlmann and Tortuga Logic...I Mean Cycuity

I was in San Francisco for the RSA security conference. On Monday, it has tutorials…

• 2 min read
tortuga logic , cycuity , common weakness enumeration

RF /マイクロ波設計

μWaveRiders:新しいPythonライブラリは、Cadence AWR Design Environmentで高レベルのAPIを提供します

新しいPythonライブラリは、Pythonのコーディング規則により厳密に準拠したコマンド構造を使用して、PythonとAWRソフトウェア間のインターフェイスを容易にするために作成されました…

• less than a min read
RF Simulation , Circuit simulation , AWR Design Environment , Graphing measurements , awr , Graphs , Tips/Tricks , Circuit Design , microwave office , japanese blog , measurements , Visual System Simulator(VSS)

RF Engineering

μWaveRiders: New Python Library Provides a Higher-Level API in the Cadence AWR Design…

A new Python library has been written to facilitate an interface between Python and…

• 5 min read
RF Simulation , Circuit simulation , AWR Design Environment , Python , API , pyawr utilities , awr , RF design , VBA , microwave office , Visual System Simulator (VSS) , scripting

Breakfast Bytes

June Update: CHIPS, Minis, and DI Water

My monthly update normally occurs on the last Friday of the month. But for June,…

• 4 min read
Intel , mini , di water , motorcycles , chips act

Verification

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

• 5 min read
Dynamic Power Analysis , xcelium , power

Breakfast Bytes

Sunday Brunch Video for 17th July 2022

https://youtu.be/ogP4BoGLEW4 Made with Lumen5 Monday: Cadence Acquires Future Facilities…

• less than a min read
sunday brunch

System, PCB, & Package Design 

Ascent: Training Insights: Managing Design Variations in Allegro System Capture

Assembling the board is one of the last yet crucial steps in the PCB development…

• 4 min read
System Capture , 17.4 , design variant , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Allegro

Breakfast Bytes

Cadence and MathWorks Announce Flow from MATLAB to RTL

Today in Yokohama at CadenceLIVE Japan, Cadence announced a new MATLAB/Stratus flow…

• 4 min read
Mathworks , Stratus , HLS , Matlab

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Cadence Celsius Thermal Solver: A Complete Thermal…

This blog introduces Cadence Celsius Thermal Solver, the industry’s first complete…

• 5 min read
Sigrity and Systems Analysis , CFD , Celsius Thermal Solver , thermal management , PDN , Power Dissipation , Thermal Basics , 3DIC , IC package design , Computational Fluid Dynamics , PCB design , Air Cooling , FEA

カスタムIC／ミックスシグナル

Spectre Tech Tips: 精度101

Spectreを含むアナログ回路シミュレータは、求める測定値に応じてシミュレータのパラメータをパッケージとして切り替え、最適な精度と性能のバランスを得るための精度モードが用意されています…

• less than a min read
Analog Simulation , accuracy , analog , vabstol , Spectre , Simulators , iabstol , japanese blog , reltol , spectre x , Spectre X Simulator

Breakfast Bytes

DAC 2022: Day 3

On to day 3 and the final day that I will be posting about. My posts on the first…

• 12 min read
bespoke silicon , DAC , 49dac , Design Automation Conference
CDNS - Fix Layout Hompage