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Digital Design: Wondering What to Do During the Winter Staycation? How about Learning Something New?

VNelson

We just recently released a training course that we are excited to tell you about.

The course is RTL-to-GDSII Flow.

This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with.

You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in VHDL or…
- 15 Dec 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Running RAVEL Rules from Command Line

Niharika1

In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI. The RAVEL rules that you write can be run from command line or Graphical User Interface (GUI) of Allegro® PCB Editor. You can also run these rules from Allegro&re...
- 15 Dec 2020
Digital Design: SSV 20.2 Base Release Now Available

SSV Release Team

The SSV 20.2 production release is now available for download at Cadence Downloads. For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the SSV 20.2 release, see ...
- 15 Dec 2020
System, PCB, & Package Design : IC Packagers: Comparing Design Versions to Find Physical Changes

Tyler

ECOs. Without them, the lives of designers would be so much easier! Imagine a world where the original requirements you were given never changed throughout the design. Unfortunately, such a world, as we know, does not exist. How, then, can you track ...
- 15 Dec 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy

Claudia Roesch

Fast growing markets like 5G, automotive, and IoT are driving the development of advanced semiconductor technologies and silicon-integrated circuits. In particular, the high cutoff frequency of advanced CMOS and Silicon-Germanium (SiGe) bipolar devices allow the integration of millimeter-wave circuits with good high-frequency performance and high integration level at moderate mask costs.
- 15 Dec 2020
Breakfast Bytes: Instruction Decoders: RISC vs CISC

Paul McLellan

In my post The Start of the Arm Era I said that it feels like something significant is changing. There's something Arm-y in the air. Suddenly Arm is faster than all x86 processors except the highest end of AMD's line. But why now? The three b...
- 15 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Conserve Power— Virtuoso Power Managerのセットアップ

Custom IC Japan

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso Power Managerの機能と可能性をご紹介します。今後のこのミニ・シリーズの投稿にご注目ください。良い設定を満足のいく結末と間違えないでください - 多くの駆け出しの作家は、本当の物語が始まる準備ができただけのところで物語を終わらせてしまいます。 Stanley Schmidt このミニ・シリーズの最初のブログはすでにお...
- 14 Dec 2020
Digital Design: Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the Rescue

sakshin

This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow.
- 14 Dec 2020
Life at Cadence: My Life at Cadence: Dimitra Papazoglou

Laura Charabot

Cadence embraces multiculturality and diversity as an important part of our One Team culture. This becomes very clear looking at our offices across the globe and in Europe, where we are proud to count more than 1,000 talented employees coming from ma...
- 14 Dec 2020
Breakfast Bytes: Avoiding PCB Respins with Better Computational Software

Paul McLellan

When I first came to the US, I started at VLSI Technology supporting a project called Bagpipe, mostly by getting the big Versatec plotter that VLSI had purchased to work at full speed and to spool jobs. Bagpipe was a chip for the future Mac...
- 14 Dec 2020
Breakfast Bytes: Sunday Brunch Video for 13th December 2020

Paul McLellan

https://youtu.be/ZcYIbkrHSv4 Made by my Christmas tree (camera Carey Guo) Monday: CadenceCONNECT: Mission Critical - Tom Beckley's Keynote Tuesday: How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs Wednesday: Photonics: How...
- 13 Dec 2020
Life at Cadence: Highlighting Our Girl Geeks at Cadence!

Mary Kasik

Last month, Cadence partnered with Girl Geek X for the first time, hosting a virtual, global event that featured five technical women at Cadence who provided thought leadership on a variety of inspiring topics. This event was a great way to highlight...
- 11 Dec 2020
System, PCB, & Package Design : BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and Simulation

Sarbjit

Legacy material editors supported different file formats leading to inconsistencies across PCB and package substrate design applications. This drawback due to inconsistency is now overcome by the new Material Editor that uses a ...
- 11 Dec 2020
Breakfast Bytes: HBI, a New Standard to Connect Your Chiplets

Paul McLellan

It is not very well-known how involved Cadence is in establishing standards. Recently, in my post Cadence and Standards...and a New Codec for Your Phone, I wrote about this and about one particular standard, the new EVS (Enhanced Voice Services) code...
- 11 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso ADE Verifierでの検証 - 信頼性の方法!

Custom IC Japan

数年前、私たちは改善および刷新されたVirtuoso ADE Verifierをリリースしました。その様々な利点に親しんで頂いているに違いないと確信しています。ビデオ、ドキュメント、過去のブログといった様々なチャンネルを通じて既に共有していることを要約すると、Virtuoso ADE Verifierはアナログおよびミックスシグナル設計の実装および要件ドリブン検証により、様々な検証段階でプロジェクトフローを管理するのに役立ちます。これに加え、検証プロジェクトにおいてトップダウン、ボトムアップ、ま...
- 10 Dec 2020
Breakfast Bytes: The 2020 RISC-V Summit

Paul McLellan

The second week of December was RISC-V week, the three-day RISC-V summit (or four if you are a member since Monday was "member day"). Tuesday opened with the keynotes being broadcast live. At least, that was the plan. The video platform pre...
- 10 Dec 2020
RF /マイクロ波設計: μWaveRiders:AWR電磁界シミュレータは設計の成功のために複雑なRF/マイクロ波の構造を解析

RF Design Japan

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るためには、Su...
- 9 Dec 2020
Breakfast Bytes: Photonics: How Do You Attach Fiber to the Chip?

Paul McLellan

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have ...
- 9 Dec 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: システム解析と実装を可能にするためのライブラリ構築

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 8 Dec 2020
System, PCB, & Package Design : IC Packagers: Leaving Yourself Reminders in Your Designs

Tyler

Are you like me? Do you forget things and have a running to-do list for your designs? Would you like to leave instructions and comments for your colleagues to remind them of actions needing doing? There are many places to record this type of informat...
- 8 Dec 2020
Breakfast Bytes: How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs

Paul McLellan

Last week was the virtual event CadenceCONNECT: Photonics Contribution to High-Performance Computing. The opening keynote was by Odile Liboiron-Ladouceur who leads a team working on photonics at McGill University in Montréa...
- 8 Dec 2020
RF /マイクロ波設計: RF Design Japan: RF/マイクロ波設計のブログを開設します。

RF Design Japan

新しいRF / Microwave Designブログシリーズがオンラインのケイデンスコミュニティに参加し、日本の読者にケイデンスAWR RF製品のショーケースとしてサービスを提供しています。このブログは、RF /マイクロ波MMIC、PCB、およびモジュールの設計者が関心を持っている問題に焦点を当てており、高周波電子機器、リリース情報、技術記事の日本語翻訳に関連する今後のローカルおよびオンラインイベントを紹介しています。新しいブログカテゴリには、Communityページの左側にある灰色のパネ...
- 8 Dec 2020
カスタムIC／ミックスシグナル: Virtuosity: Conserve Power— Virtuoso Power Managerの前置き

Custom IC Japan

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso Power Managerの機能と可能性をご紹介します。今後のこのミニ・シリーズの投稿にご注目ください。電力消費は、常に電子設計における最優先事項です。消費は、回路で使用される電力だけではなく過熱を防ぐための回路のモニタリングにも関係します。電子製品のバッテリー寿命が、成功への決定的要因になり得ます。設計者は、デザインの性能に影...
- 7 Dec 2020
Life at Cadence: When One Door Closes...Opening New Doors with Cadence Retool-to-Work

BonnieW

I love the second half of this famous quote by Alexander Graham Bell “When one door closes another door opens; but we often look so long and so regretfully upon the closed door that we do not see the one which has opened for us.” With the...
- 7 Dec 2020
Verification: Xcelium Provides 3X Performance Increase for StreamDSP's FPGA-Based Defense IP

Ankur J

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to…
- 7 Dec 2020

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