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Analog/Custom Design: Knowledge Booster Training Bytes - How to Model Analog Blocks with Verilog-AMS Wreal Modeling?

Jaseem TM

Do you know you can speed up analog or mixed-signal simulations with digital mixed signal technology? View this blog to know more.
- 13 Dec 2022
Breakfast Bytes: Using Clarity 3D Solver to Analyze 3D Packaging

Paul McLellan

3D packaging is becoming an increasingly popular solution for protecting and packaging sensitive electronic components. However, designing and analyzing 3D packaging can be a complex and time-consuming process. That's where Clarity 3D Solver comes ...
- 13 Dec 2022
Digital Design: Knowledge Booster Training Bytes - In-Design Pegasus Signoff Verify Design (SVD)

JentilTom

In-Design Pegasus Signoff Verify Design (SVD) integrates Pegasus Signoff and Pegasus SmartVerifyTM with Innovus. These checks help you maintain your designs DRC and LVS clean through the design cycle and help achieve zero DRC and zero shorts out of Innovus, thus saving overall development time.
- 12 Dec 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

The year 2022 may be coming to an end, but Cadence Fidelity CFD never stops. Here's our weekly review of what we've got going on. From the Blogs Fidelity CFD Mesh Adaptation that Respects Geometry and Reduces Runtime Mesh adaptation can be u...
- 12 Dec 2022
Life at Cadence: Intelligent System Design Ecosystem Development Is More Important than Ever

Corporate

Electronic Design Automation (EDA) companies have long concentrated on ecosystem development to ensure successful design practices for their customers. Cadence has many partnerships—with foundries, standards bodies, channel partners, industry ...
- 12 Dec 2022
Digital Design: Training Insights - What Is IR drop? Is it Possible to Run IR-drop Analysis Using Innovus?

P Saisrinivas

IR drop is the difference between two endpoints of the conducting wire during a current flow, where the resistance of the conductor will decide the drop percentage. IR drop is also known as the Voltage drop.

So, this Voltage drop in the metal wires weakens the power routing before the actual voltage reaches the power pins of the standard cells, which can affect the speed of the standard cells and the chip…
- 12 Dec 2022
Breakfast Bytes: ChatGPT: "A New Technology Adjusts Your Thinking About Computing"

Paul McLellan

Do you know what ChatGPT is? There's a good chance that the answer is "no" because, last time I looked, mainstream media like the New York Times or the Washington Post have had zero articles about it. But on Twitter, over the last week ...
- 12 Dec 2022
Computational Fluid Dynamics: Play by the Rules – Identify and Fix Mesh Quality Issues Right Away!

Veena Parthan

The physical models, the solver algorithm, the grid type, the available computer resources, desired outputs, desired level of accuracy, organization's best practices truly determine a grid's acceptability. Using Fidelity Pointwise’s Rules command, one can monitor and verify the specified grid requirements at any time during the meshing process.
- 12 Dec 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Are You Telling Me I Can Auto-Generate a Package Schematic From a Package Layout?

VRF Knight

Yes, you heard that right! You can now auto-generate a package schematic from a package layout with a snap of a finger! With Virtuoso RF Solution, there are all kinds of automations that allow you to have a connectivity-driven design. You can verify the connectivity by the top-level analog simulation and functional verification to make sure your netlist and results are within your expectation. In addition, verify your…
- 12 Dec 2022
Breakfast Bytes: Sunday Brunch Video for 11th December 2022

Paul McLellan

https://youtu.be/6urbyyIDtZg Made at Koi Palace Contempo (camera Carey) Monday: CadenceLIVE Europe 2022 Tuesday: Axiomise: Formal, Especially for RISC-V Wednesday: Advanced Auto-Routing for TSMC InFO Technologies Thursday: Breakfast Bytes Guide ...
- 11 Dec 2022
Breakfast Bytes: Berlin Technik Museum and the Zuse Z1

Paul McLellan

The Berlin Technical Museum, officially the Deutsches Technik Museum, has a big collection of trains, planes, and ships, not to mention textiles, luggage manufacturing, jewellery manufacturing, and more. But I'm going to focus on the computing se...
- 9 Dec 2022
カスタムIC／ミックスシグナル: Virtuosity: カスタムIC設計フロー／手法―ポストレイアウト回路シミュレーションとGDSII生成

Custom IC Japan

カスタム／ミックスドシグナル設計における現在の課題は、高速でシリコン精度の高い手法を持つことです。このブログ・シリーズでは、カスタムICの設計フローと手法の段階についてご紹介します。この手法は、設計プロセスを通じてスピードとシリコン精度を最大化することで、これらのIC設計の作成における予測可能性という主要な課題に直接対処します。また、この手法は、アナログ、カスタム・デジタル、RFの主要な設計領域をカバーし、デジタル・スタンダードセル・ブロックとの統合をサポートします。設計フローの段階下図は、...
- 8 Dec 2022
Life at Cadence: Renault Is Lowering Their Carbon Footprint with Cadence

Corporate

The automotive industry is shifting its focus to reducing CO2 emissions from its vehicles, and it’s no surprise, given the current state of the environment. Renault is a world leader in the automotive market, working on internal combustion engi...
- 8 Dec 2022
Breakfast Bytes: Breakfast Bytes Guide to Berlin

Paul McLellan

I was in Munich for CadenceLIVE Europe and took that opportunity to write Breakfast Bytes Guide to Munich. The next day, my wife and I took the train to Berlin. Somehow, I'd never been to Berlin before. There is clearly a lot of history here...
- 8 Dec 2022
PCB設計／ICパッケージ設計: BoardSurfers: Constraint Setの利用によりコンストレイントを効果的に管理する

SPB Japan

コンストレイント(Constraint)とは、デザイン内のネット、ピン、ビアなどの物理オブジェクトに適用されるユーザー定義のプロパティ、またはルールです。オブジェクトには、そのタイプと動作に基づき適用できるコンストレイントが多数あります。例えば、ネットがデザインで遵守しなければならない最小線幅および最大線幅の値("Line Width")を定義できます。また、すべてのテストピンがテストビアから維持する必要がある最小距離や、Single-line Impedance やProp...
- 8 Dec 2022
Digital Design: Training Insights - Dude, Where's My Software?

VNelson

When you go to download the latest version of Innovus, Genus or Joules our Cadence download site, downloads.cadence.com, you will notice a big change. Instead of the expected INNOVUS221 or GENUS221 or JOULES221 releases, you will find instead DDI221 which includes the 22.1 versions of all three tools.
- 7 Dec 2022
Analog/Custom Design: Knowledge Booster Training Bytes - Enhance Layout Productivity with Virtuoso CLE

rbaby

Do you know you can work in parallel with Virtuoso Concurrent Layout? Click here to know more.
- 7 Dec 2022
Life at Cadence: Software-Defined Vehicles: The Automotive Revolution with Silicon at its Heart

Ben Gu

The automotive sector is undergoing immense change. The retirement of the internal combustion engine (ICE) in favor of electrified powertrains and a shift towards autonomy has provided carmakers the opportunity to reimagine and redefine the entire a...
- 7 Dec 2022
Breakfast Bytes: Advanced Auto-Routing for TSMC InFO Technologies

Paul McLellan

At the recent TSMC OIP Symposium, John Park presented Advanced Auto-Routing for TSMC InFO Technologies. InFO stands for "integrated fanout" and is the lower performance, lower complexity technology for advanced packaging. For details of TSM...
- 7 Dec 2022
Analog/Custom Design: Virtuoso ICADVM20.1 ISR29 and IC6.1.8 ISR29 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR29 and IC6.1.8 ISR29 production releases are now available for download.
- 7 Dec 2022
The India Circuit: Tulasi Narayanaswamy: Against All Odds

Asim Khan

Tulasi's Story Tulasi is a brilliant young woman who has the aspiration, grit, and determination to be successful. Coming from a low-income family living in a remote village in Karnataka, Tulasi had limited opportunities and access to higher educ...
- 6 Dec 2022
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: PoPの頂点に立つ！Virtuosoでパッケージのフットプリントをエクスポートすることによって

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのI...
- 6 Dec 2022
Computational Fluid Dynamics: Fidelity CFD Mesh Adaptation that Respects Geometry and Reduces Runtime

Veena Parthan

Fidelity CFD mesh adaptation technique respects geometry, improves mesh quality, adapts to the near-wall shear layers, and reduces run-time for improved CFD solutions.
- 6 Dec 2022
Breakfast Bytes: Axiomise: Formal, Especially for RISC-V

Paul McLellan

I recently talked to Ashish Darbari, the CEO of Axiomise. They are based in London, where Ashish ended up having bounced around the world. But more of that later. I also discovered that he would be presenting at CadenceLIVE In Munich the followi...
- 6 Dec 2022
System, PCB, & Package Design : BoardSurfers: Sharing Pulse-Managed Data with Third-Party Layout Partners

Adam Fuchs

Modern electronic designs have many stakeholders involved in the process. It is not uncommon for schematic drawing and pre-design simulation to be done in-house while the layout is handled by a third-party design partner. Allegro® Pulse not only ...
- 6 Dec 2022

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