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Latest Blog Posts

  • Digital Design Highlights: New Training, Blogs, Videos, and Badges 2025

    Digital Design: Digital Design Highlights: New Training, Blogs, Videos, and Badges 2025

    ulrike
    ulrike

    As another year came to a close, we reflect on our most popular blog posts and provide a summary of the key developments in the education sector.

    In 2025, we expanded our Digital Design and Signoff Community with 31 new blog posts, delivering fresh insights and valuable training content. Additionally, we hosted two engaging webinars covering expert knowledge and practical takeaways. If you missed them, don't worry—you…

    • 14 Jan 2026
  • Bluefins Whale-Inspired Propulsion System to Reduce Operating Costs by 20%

    Computational Fluid Dynamics: Bluefins Whale-Inspired Propulsion System to Reduce Operating Costs by 20%

    Veena Parthan
    Veena Parthan
    Bluefins develops a wave energy conversion technology, inspired by the fins of whales, to reduce GHG emissions and fuel operating costs by 20%
    • 13 Jan 2026
  • プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

    Cadence Japan: プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

    Cadence Japan
    Cadence Japan
    ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。
    • 8 Jan 2026
  • Cadence ASK: 2025 Highlights and What’s Next!

    Learning and Support: Cadence ASK: 2025 Highlights and What’s Next!

    ulrike
    ulrike
    As we step into 2026, let's celebrate the advancements and shared successes in 2025 that made Cadence ASK smarter, more insightful, and more connected than ever. Your Go-to Resource for Answers We kicked off 2025 by addressing your most fre...
    • 8 Jan 2026
  • Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

    Corporate News: Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

    Corporate
    Corporate
    Cadence, a global leader in electronic system design, is celebrating 20 years in Pune as a core research and development hub. This milestone marks two decades of sustained investment and innovation in the region. Established in 2006 by Tensilica, now...
    • 6 Jan 2026
  • Did You See? Mandarin Subtitles Are Live for Innovus Training—Here’s Your Start

    Digital Design: Did You See? Mandarin Subtitles Are Live for Innovus Training—Here’s Your Start

    P Saisrinivas
    P Saisrinivas

    I don't speak many languages, but I happily watch web series in different languages. Do you know how?

    I believe many of us do the same, and we all know the answer: it's with the help of subtitles. They help us to watch any series or movie to understand them easily in our preferred language. Keeping this in mind, what if we expanded the idea of adding subtitles in different languages to online courses? Recently, …

    • 6 Jan 2026
  • Modular Magic: Accelerate Chip Design with Genus Bottom-Up Flows

    Digital Design: Modular Magic: Accelerate Chip Design with Genus Bottom-Up Flows

    Neha Joshi
    Neha Joshi

    Let's face it: tackling a modern SoC design top-down is like trying to eat a triple-layer cake in one bite—messy, overwhelming, and likely to end with frosting on your keyboard. Enter the Bottom-Up Flow in Cadence's Genus Synthesis Solution: the engineering equivalent of slicing that cake into perfect, manageable pieces (and yes, you get to eat them, too).

    But what is bottom-up flow, really? Imagine you…

    • 6 Jan 2026
  • Mini Clips, Mini Videos, Mega Crave: Why Short Reels Dominate Screens

    Digital Design: Mini Clips, Mini Videos, Mega Crave: Why Short Reels Dominate Screens

    P Saisrinivas
    P Saisrinivas

    The first thing most of us do today isn’t opening a book or a laptop; it’s unlocking our phone. Within seconds, a short reel pulls us in. It speaks our language, matches our pace, and meets us exactly where we are. That’s why short videos connect so deeply with us, and they dominate the screen, without demanding much time.

    In real life, learning often occurs in our free time or on weekends, during uninterrupted…

    • 5 Jan 2026
  • Virtuoso Studio: LPP Transparencyを用いてデザインを明瞭に表示する

    カスタムIC/ミックスシグナル: Virtuoso Studio: LPP Transparencyを用いてデザインを明瞭に表示する

    Custom IC Japan
    Custom IC Japan
    これは、Virtuoso Studio IC 25.1のリフレッシュに関する5部構成のブログシリーズの第3弾です。最も混雑したレイアウトでも簡単にナビゲートできるように設計された、もう一つの強化機能 — LPP Transparency をご紹介します。
    • 25 Dec 2025
  • ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

    Cadence Japan: ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

    Cadence Japan
    Cadence Japan
    ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。
    • 22 Dec 2025
  • 3D-IC Market Outlook: Technology Roadmaps, Readiness, and Design Implications

    Corporate News: 3D-IC Market Outlook: Technology Roadmaps, Readiness, and Design Implications

    Reela Samuel
    Reela Samuel
    The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver...
    • 22 Dec 2025
  • Cadence 3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts

    Corporate News: Cadence 3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts

    Reela Samuel
    Reela Samuel
    As scaling at advanced nodes becomes increasingly constrained by cost, yield, and power density, semiconductor innovation is shifting decisively toward 3D-IC technologies, chiplets, and heterogeneous integration. Across AI infrastructure, cloud compu...
    • 19 Dec 2025
  • 3D-IC Test and Reliability: KGD Strategies, Access Architecture, & Failure Mode

    Corporate News: 3D-IC Test and Reliability: KGD Strategies, Access Architecture, & Failure Mode

    Reela Samuel
    Reela Samuel
    3D-IC technology is redefining how advanced systems are built, but it also introduces a new class of challenges in 3D-IC testing and reliability. As multi-die and chiplet-based systems replace monolithic SoCs, achieving predictable yield, comprehensi...
    • 18 Dec 2025
  • Story of Badavath Shiva Kumar - Cadence Scholarship Program

    The India Circuit: Story of Badavath Shiva Kumar - Cadence Scholarship Program

    Asim Khan
    Asim Khan
    Shiva Kumar's journey from the rural village of Mandamaari in Telangana’s Mancherial district is one of grit and grace. Shiva lost his father when he was just six months old. Raised by his mother—a daily wage laborer—and maternal gr...
    • 18 Dec 2025
  • Accelerate Your Design Signoff with Cadence Voltus Training Kit

    Digital Design: Accelerate Your Design Signoff with Cadence Voltus Training Kit

    Vinod Khera
    Vinod Khera
    By Ronen Stilkol, Senior AE Architect In the rapidly evolving world of semiconductor design, signoff challenges are growing due to increasing complexity, shrinking technology, a rising number of transistors, and the adoption of 3D-IC technology. Add...
    • 17 Dec 2025
  • Microwave Office 用の村田製作所の新しいライブラリ

    RF /マイクロ波設計: Microwave Office 用の村田製作所の新しいライブラリ

    RF Design Japan
    RF Design Japan
     表面実装キャパシタを含むすべての電子部品は、その物理的構造(リード、内部構造、PCB 配線)により、理想的な電気的動作から逸脱する望ましくない寄生特性を持っています。特に高周波数では、これらの寄生特性によって、信号の歪み、ノイズ(クロストーク)の増加、帯域幅の減少、タイミングエラー、電力損失、増幅器の不安定性などの問題が発生します。 製品開発の設計段階でシステム性能への影響を適切に処理できるように、部品の寄生成分を正確に表す高周波モデルを使用して、これらの影響を回路解析に組み込むことが重要です...
    • 17 Dec 2025
  • Virtuoso Studio IC25.1 ISR3 Now Available

    Analog/Custom Design: Virtuoso Studio IC25.1 ISR3 Now Available

    KomalJohar
    KomalJohar
    Virtuoso Studio IC25.1 ISR3 production release is now available for download.
    • 17 Dec 2025
  • New Murata SMD Library for Microwave Office Support

    RF Engineering: New Murata SMD Library for Microwave Office Support

    StandingWaves
    StandingWaves
    Due to their physical construction (leads, internal structure, PCB traces), all electronic components, including surface mount capacitors, have unwanted parasitic characteristics that deviate from their ideal electrical behavior, especially at high f...
    • 17 Dec 2025
  • Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

    Corporate News: Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

    Corporate
    Corporate
    Delivering the next wave of chiplet innovation, Cadence has successfully taped out its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution, achieving industry-leading 64Gbps per-lane speeds on the advanced TSMC N3P process. As ...
    • 17 Dec 2025
  • Training Insights Accelerated Learning–The More You Know, the Faster You Go

    Learning and Support: Training Insights Accelerated Learning–The More You Know, the Faster You Go

    Pazhani
    Pazhani
      We know your time is valuable. That’s why we created the Online Accelerated Learning option. You focus on what's new and skip what you already know—saving you time—meaning you reach your training goals faster.&n...
    • 17 Dec 2025
  • Virtuoso Studio: Streamlining the Design Review Process

    Analog/Custom Design: Virtuoso Studio: Streamlining the Design Review Process

    Parula
    Parula
    This blog covers how to overcome challenges that can arise in the Design review process due to accessibility, maintenance, and relevance by using the Virtuoso-based Design Review feature.
    • 16 Dec 2025
  • 3D-IC in AI, HPC, and 5G: Bandwidth, Latency, and Energy per Bit Advantages

    Corporate News: 3D-IC in AI, HPC, and 5G: Bandwidth, Latency, and Energy per Bit Advantages

    Reela Samuel
    Reela Samuel
    3D-IC technology is rapidly becoming the backbone of next-generation compute systems as traditional 2D scaling reaches physical and economic limits. Momentum is accelerating across industry, propelled by high-bandwidth memory (HBM) stacking, hybrid ...
    • 16 Dec 2025
  • Don’t Let Bugs Slip Through Your RTL Design!

    Verification: Don’t Let Bugs Slip Through Your RTL Design!

    Ankita Soni
    Ankita Soni

    To validate your RTL design, are you still relying solely on simulation? Is there anything else that needs to be done to validate it further?

    Simulation has been a cornerstone of hardware verification for decades. Its ability to generate random stimuli and validate RTL across diverse scenarios has helped engineers uncover countless issues and ensure robust designs. However, simulation is inherently scenario-driven, which…

    • 16 Dec 2025
  • 業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

    Cadence Japan: 業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

    Cadence Japan
    Cadence Japan
    CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。
    • 15 Dec 2025
  • Integrity 3D-IC Course Updated for Version 25.1

    System, PCB, & Package Design : Integrity 3D-IC Course Updated for Version 25.1

    Vince Kim
    Vince Kim
    Unlocking Advanced 3D-IC Design: The Updated Integrity 3D-IC Course The semiconductor industry is rapidly evolving, and so are the tools and methodologies that enable cutting-edge designs. To keep pace with these advancements, the Integrity 3D-IC cou...
    • 15 Dec 2025
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