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カスタムIC／ミックスシグナル: Virtuosity: 先端ノード用デバイスレベル配線 ‐ Generate Trunksの使用

Custom IC Japan

このVirtuoso®デバイスレベル配線のブログシリーズの2回目以降では、トランク（幹線）とツイッグ（枝配線）がどのようにツリー構造を構築するかについて説明します。今回は、カスタマイズしたデバイスレベル配線を実現ための骨子となる、Trunk Generation機能の詳細を説明します。従来ノードから先端ノードへの移行ともなって、設計はますます構造化され、グリッドベースになっています。以下は、今日、先端ノードで見られる配置後のデバイスレベル設計の例です。ケイデ...
- 5 Jun 2020
Breakfast Bytes: Modeling with Water

Paul McLellan

A couple of years ago I wrote a post using the famous quote by statistician George Box: All Models Are Wrong; Some Are Useful. In that post, I discussed paper and plastic airplanes, but mostly I talked about modeling in computers, and especially wha...
- 5 Jun 2020
Analog/Custom Design: Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional Verification Flow

Rick Sanborn

What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made possible with the latest Xcelium Mixed-Signal technologies from Cadence.
- 4 Jun 2020
Breakfast Bytes: Four More Waves: 5G, Cars, Clouds, IoT

Paul McLellan

Earlier in the week, I did a sort of bait and switch, introducing the five waves and then talking about just one of them. In that post, The Five Waves: AI, 5G, Cars, Clouds, IoT, I just covered the first wave of AI and machine learning. To...
- 4 Jun 2020
PCB設計／ICパッケージ設計: 2019年10月リリース、OrCAD/Allegro 17.4-2019の新機能ハイライト

SPB Japan

洗練された先進的なバージョンであるOrCAD/Allegro 17.4-2019がリリースされました。使いやすさの追求と共に、生産性向上のための新機能が数多く実装されています。回路図から基板、基板から製造へとつながるデータ反映のプロセスは最適化され、より直感的で使いやすいフローが実現しました。したがって、このリリースは、電気系CADに携わるすべての人々に(回路設計者でもレイアウト設計者でも、あるいはライブラリとパーツの管理・作成担当者や、電気系CADプロセスの管理担当者であっても)必ず役立つ機...
- 3 Jun 2020
カスタムIC／ミックスシグナル: Virtuosity: 先端ノード用デバイスレベル配線 ‐ Finish Trunkの使用

Custom IC Japan

Virtuoso® Layout Suiteにはデバイスレベルの配線分野に関してユーザーからのご希望に応じて開発された新しい優れた機能が多数存在します。特に最近リリースされた複雑化する先端ノード設計向けの新機能、—手動配線、配線支援から配線作業の自動化の強化など、さまざまな機能をこのブログのシリーズでご紹介していきます。このブログを検索し、過去数ヶ月で登場した新しい機能についてご覧ください。 Finish Trunkコマンドを活用していらっしゃいますか。また、その機能をご存...
- 3 Jun 2020
System, PCB, & Package Design : BoardSurfers: DRC Browser – A One-Stop Solution for DRC Management

Monika

Design rule checks are essential to ensure the functionality, reliability, and manufacturing yield for a design. You run DRCs several times during the design cycle to validate the design. If I say auditing design rules is an intense and time-c...
- 3 Jun 2020
定制IC芯片设计 : Virtuosity: Auto Device Array - A One-Stop-Shop for Modgens

Aneesh Shastry

在本博客中，我将讨论以下这样的功能，一个个人喜爱的功能- the Auto Device Array 一个简单，直观且功能强大的界面，用于创建和自定义Modgens。
- 3 Jun 2020
System, PCB, & Package Design : IC Packagers: Count Your Fingers (Without Using Your Toes)

Tyler

Let’s talk about wire bonding today! More specifically, the unique labels assigned to every bond finger in your design and how these are import for documentation and your bonding engineer. Bond finger labels are like physical pin numbers on you...
- 3 Jun 2020
Breakfast Bytes: Artificial Intelligence...and Artificial Performance

Paul McLellan

Do you know what this is? It's a benchmark. The Ordnance Survey (OS) of Britain created around half-a-million of these, and the horizontal line at the top is known for each one as a height above sea-level. Actually, it is a height above...
- 3 Jun 2020
Academic Network: Digital Design and Signoff Training Deep Dive: Part 1 – Synthesis and Test

Kira Jones

This blog series will the break down the top 15 Online Training courses among students and professors into their different technical areas and share the supporting courses that go along with them, starting with Digital Design and Signoff. D...
- 2 Jun 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Thinking Outside the Chip: Overcoming RFIC and RF Module Design Challenges

Kim Khoury

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts…
- 2 Jun 2020
Breakfast Bytes: TSMC: N7, N6, N5

Paul McLellan

TSMC has such a large market-share of the foundry business that their roadmap is the de facto roadmap for many of the largest fabless semiconductor companies. In a normal year, I look forward to the TSMC Technology Symposium in April. It is the main ...
- 2 Jun 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: TILP! 什么是TILP?

kgjudd

过去的38年，我一直致力于IC版图设计！在业内不断推出Cadence的新产品，让我积累了宝贵的经验。在这篇博客中，我要谈谈另一创新产品--Virtuoso RF解决方案及其基本概念。对于不了解Virtuoso RF解决方案的电路封装设计师，或是第一次在Virtuoso进行封装设计的IC版图设计师而言，这些概念都是必须掌握的。
- 1 Jun 2020
Breakfast Bytes: The Five Waves: AI, 5G, Cars, Clouds, IoT

Paul McLellan

In Cadence's recent earnings call, Lip-Bu Tan, our CEO, talked about the five waves that are hitting us simultaneously. Here's what he said: Yes. John, it's a good question. First of all, I'm excited about this industry, because it's very unusual t...
- 1 Jun 2020
Verification: Improving Tests Efficiency Using Coverage Callback

teamspecman

When you go to the store, you walk until you get there, stop, get your groceries, and go back home. You do not start circling around the block for few rounds. You do not say “if I walk around the block really fast, I can save time”. It is clear that if you avoid circling the block at first place – you will save even more time.

Why don’t we adopt the same rationale in the verification process? Instead…
- 31 May 2020
Breakfast Bytes: Sunday Brunch Video for 31st May 2020

Paul McLellan

www.youtube.com/watch Made in "Paris" (camera Carey Guo) Monday: Memorial Day Tuesday: Simon Butler's Fireside Chat with Jim Hogan Wednesday: Automotive Ethernet Thursday: 5G: Connecting All the Things Friday: First US Manned Launch Sin...
- 31 May 2020
Breakfast Bytes: First US Manned Launch Since 2011...Not Yet

Paul McLellan

On Wednesday, SpaceX and NASA planned the first launch from the USA of a manned spacecraft in nearly a decade (US-built, too). The last launch, in 2011, was the final flight of the Space Shuttle. It was back in 1981, when the shuttle first flew,...
- 29 May 2020
カスタムIC／ミックスシグナル: Virtuosity: Automated Device Placement and Routing - デバイスグループとトポロジーの特定

Custom IC Japan

前回に続き、Virtuoso® 自動デバイスレベル配置配線シリーズの2回目のBlogをご覧ください。前回は、アナログとフルカスタムデザインでの完全自動型のデバイスレベル配置配線ソリューションの必要性についてお話しました。今回は、このプロセス中の重要なステップである、「デバイスグループと、配置配線用のトポロジーの特定」について掘り下げていきます。課題アナログ設計の核となるものは、正確性とマッチングです。ゲイン、消費電力、Voltage スイング、あるいはノイズといった様々な...
- 29 May 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso の自動デバイスレベル配置配線ソリューションのご紹介

Custom IC Japan

半導体産業は、IC デザイン向けの電子設計自動化ソフトウェア(EDA)に長期に渡り依存してきました。長年に渡る半導体産業の進化に合わせて、EDA ツールも進化してきました。しかしながら、アナログ、フルカスタム用EDA ツールの進化は、デジタル用ツールのそれに比べて、劇的ではありませんでした。この背景にはいくつかの理由があります。レイアウトの自動生成を難しくした最も重要なものに、自動生成のレイアウトをマニュアルレイアウトのクオリティに一致させること。加えてアナログデザインでは、デジタルデザイ...
- 29 May 2020
Digital Design: Library Characterization Tidbits: Overriding the One-Sigma Rule of Liberty for LVF Modeling

AbhaRawat

As per Liberty specification, Liberty Variation Format (LVF) modeling is always done at one-sigma. However, did you know that Liberate Variety supports unique settings for characterization and LVF modeling?
- 28 May 2020
Breakfast Bytes: 5G: Connecting All the Things

Paul McLellan

Over the last few weeks, each Thursday has been Telecom Thursday (like Taco Tuesday but with guacamobile). Well, except for last week since Cadence had a surprise 4-day holiday weekend announced at the last minute. 1G Mobile: AMPS, TOPS, C-450, Rad...
- 28 May 2020
Breakfast Bytes: Automotive Ethernet

Paul McLellan

Automotive networking is perhaps the latest application area for Ethernet. But Ethernet in some form has been going for nearly 50 years. Let's start with a little history. History Ethernet really started in 1971, although it was called AlohaNet. It ...
- 27 May 2020
System, PCB, & Package Design : BoardSurfers: Allegro In-Design Coupling Analysis: Crosstalk Mitigation without Models

Shirin Farrahi

Just as social distancing minimizes human contact to prevent the spread of disease, PCB spacing constraints minimize coupling between traces to prevent crosstalk problems for drivers and receivers. In cases where a safe distance cannot be maintained,...
- 26 May 2020
System, PCB, & Package Design : IC Packagers: Keep Fan-Out Routing Aligned During ECOs

Tyler

When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tier...
- 26 May 2020

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