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Digital Design: Accelerating Silicon Success with Cadence’s Digital Full Flow

sakshin

Cadence's Digital Full Flow delivers RTL-to-GDSII convergence with industry-leading PPA and productivity.
- 5 Nov 2025
SoC and IP: Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Joe C

Modern compute systems have evolved beyond reliance on a single dominant interface. Today, they're increasingly defined by their ability to support multiple high-speed protocols concurrently—including PCIe, Ethernet, and others. This shift toward multi-protocol capability is fundamentally reshaping how we architect intelligent edge AI systems, especially as inferencing workloads grow more distributed, data-intensive…
- 5 Nov 2025
System, PCB, & Package Design : BoardSurfers: Training Insights: Automating Artwork Configuration in PCB Editor

anandd

The Artwork Configuration feature of Allegro X PCB Editor in Release 24.1 automates film record creation to streamline Gerber generation, letting designers save a standard artwork setup and reuse it across multiple projects, saving time and improving consistency.
- 3 Nov 2025
Life at Cadence: Empowering the Next Generation of Engineers: UKESF Student Bursary Event 2025

Madhuparna Datta

Electronics lies at the heart of today's technological revolution, fuelling innovation across every sector. To keep this momentum going, the demand for skilled and passionate engineers continues to grow and the first step in meeting this need is to n...
- 3 Nov 2025
Cloud: Revolutionizing Chip Design in the Cloud

Iris Zheng

Cadence OnCloud Managed Cloud Service In today's fast-paced semiconductor industry, engineering teams are under pressure to deliver complex designs in a compressed timeframe. Traditional on-premises infrastructure often struggles to keep up with ...
- 31 Oct 2025
Artificial Intelligence (AI): Arm and Cadence Showcase AI System Collaboration at AI Infra Summit 2025

ShrutiAnand

At the AI Infra Summit 2025 in Santa Clara, California, Arm's VP of Marketing for the Infrastructure line of business, Eddie Ramirez, and Cadence's VP of Research & Development, Ravi Venigalla, came together to spotlight a transformative...
- 30 Oct 2025
Academic Network: Spotlight: Cornell Custom Silicon Systems

Kira Jones

Written by Daniel Kaminski, Cornell Custom Silicon Systems Full Team Lead/Analog Subteam member, and Vayun Tiwari, Cornell Custom Silicon Systems Digital Physical Design Subteam member At Cornell University, the Custom Silicon Systems (C2S2) project ...
- 30 Oct 2025
Analog/Custom Design: Virtuoso Studio: A Fresh Look - Redefining Your Design Experience

Vipin Singh

Virtuoso Studio IC 25.1 brings a modern refreshed interface designed for comfort, clarity, and efficiency. With updates like the new Dark Gray Theme, TrueType font support, enhanced LPP transparency controls, smarter notifications, and the Virtuoso Dashboard, this release blends modern design with the reliability users trust. Virtuoso Studio now offers a more intuitive and visually balanced experience—helping you stay…
- 30 Oct 2025
Verification: Regressions, Coverage Integration, and Verification Closure

ErinGrant

Don't miss this opportunity to streamline your verification flow and achieve faster, higher-quality results. Join Cadence Training for the second day of this extended webinar series: Regressions, Coverage Integration, and Verification Closure—Streamlining Digital Front-End Design and Verification with Cadence Tools!

Navigating the Cadence front-end design and verification tool suite can be seamless when approached…
- 29 Oct 2025
System, PCB, & Package Design : Cadence OrCAD X and Allegro X 25.1 Is Now Available

SigrityReleaseTeam

The OrCAD X and Allegro X 25.1 release is now available from Cadence Downloads, delivering significant enhancements and new features. Here’s a summary of what's new: Allegro X PCB and Package Design Solutions Introduced Allegro X AI Advanced S...
- 29 Oct 2025
カスタムIC／ミックスシグナル: Virtuoso Studio がモダンな外観に刷新

Custom IC Japan

Virtuoso Studio IC25.1 で刷新された機能についてご紹介しています。快適性のための Dark Gray テーマ、可読性のための TrueType フォント、視認性のための LPP Transparency 、スマートな通知、ウィンドウ・セッション管理の Virtuoso Dashboard です。是非ご覧下さい。
- 29 Oct 2025
Verification: Streamlining Digital Front-End Design and Verification with Cadence Tools

ErinGrant

Plan, Simulate, and Debug: Streamlining Digital Front-End Design and Verification with Cadence Tools

Navigating the Cadence front-end design and verification tool suite can be seamless when approached as an integrated flow.

Join the Cadence Training team for this two-part, extended webinar series where we do just that. Get insights from industry experts who guide you through a complete, integrated verification flow
…
- 29 Oct 2025
Digital Design: Accelerating Design Closure with Cadence Certus Closure Solution v25.1

sakshin

Cadence Certus Closure Solution addresses the challenges of timing closure in advanced semiconductor design by enabling concurrent full-chip optimization and signoff with a distributed architecture, significantly reducing iteration times from days to hours.
- 28 Oct 2025
System, PCB, & Package Design : Stay Future-Ready with Cadence Licensing and Installation Community Hub

Renu Vibha

Staying ahead in PCB and IC Package design means being ready for the latest releases, which include enhanced features, evolved functionalities, and powerful improvements across the product suite. Cadence consistently delivers significant advancements...
- 28 Oct 2025
Digital Design: Smarter, Longer, Cooler: Low-Power Flow for the Devices That Never Sleep

sakshin

Cadence’s Innovus Low-Power Flow v25.1 offers a comprehensive solution for implementing and optimizing low-power designs, addressing challenges like complex power architectures and power optimization across the design flow.
- 28 Oct 2025
Corporate News: Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Corporate

Rising demand for AI infrastructure is driving faster innovation and smarter use of resources throughout the design lifecycle. Accelerated computing shortens design and simulation cycles, as well as streamlines workflows and amplifies human crea...
- 28 Oct 2025
System, PCB, & Package Design : Ascent: Training Insights: Smarter Design Reuse with Allegro X System Capture

Priyadarshini N D

In today's fast-paced electronics industry, time-to-market is critical. Engineers face the constant challenge of delivering complex designs more quickly, with fewer errors, and under tighter constraints. This is where the concept of Design Reuse ...
- 28 Oct 2025
The India Circuit: Story of Preshita Parmar - Cadence Scholarship Program

Asim Khan

Preshita Parmar began to shape a life grounded in resilience and self-belief in the corridors of a hostel in Gujarat. The only child of her father—a hostel warden—Preshita lost her mother at a young age. Her father became her anchor, offe...
- 27 Oct 2025
Verification: Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained

Felipe Goncalves

Introduction
The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols.
What Is a Flit Sequence Number?
Historically, each TLP carried an explicit sequence number, which, while contributing to…
- 23 Oct 2025
Digital Design: From Defects to Diagnostics: How DFT Transforms Chip Manufacturing

KShubham

In today’s semiconductor industry, the complexity of integrated circuits (ICs) is skyrocketing. Ensuring these chips work flawlessly isn’t just a technical challenge, it’s a business necessity. This is where Design for Test (DFT) comes in, acting as the backbone of reliable, cost-effective chip manufacturing.

What Is DFT?

DFT refers to a set of design techniques that make it easier to test manufactured…
- 23 Oct 2025
Analog/Custom Design: Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Release Team

Virtuoso Studio IC25.1 ISR2 production release is now available for download.
- 23 Oct 2025
SoC and IP: Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch

pulin

By Vijay Pawar of Cadence and Matthias Cremon of Meta
Introduction
Deploying PyTorch models on embedded devices, especially audio DSPs, presents unique challenges. To address these, Cadence and Meta have collaborated to create a robust, high-performance framework for deploying machine learning models on Cadence's Tensilica HiFi DSP family. By leveraging ExecuTorch and applying both graph-level and operator-level optimizations…
- 22 Oct 2025
Data Center: Innovation in Data Center Design and Operations: Highlights from Thésée Event

Veena Parthan

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence, and WattDesign to explore the real-world application of Cadence's digital twin technology.
- 21 Oct 2025
Corporate News: Don’t Miss the 2025 North America Open Meeting!

Corporate

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you ready to push the boundaries of what's possible in engineering and product design? The world of manufacturing is evolving faster than ever—automation, digita...
- 21 Oct 2025
Computational Fluid Dynamics: Flutter Analysis: For Safer Air Travel

Veena Parthan

Recent aviation incidents, including a commercial plane crash attributed to a loss of climb performance shortly after takeoff, have sparked worries about flight safety. These events have brought attention to problems related to malfunctioning engines...
- 16 Oct 2025

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