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Latest Blog Posts

  • Structured or Unstructured Meshes: What Works Best for Turbomachinery CFD

    Computational Fluid Dynamics: Structured or Unstructured Meshes: What Works Best for Turbomachinery CFD

    Veena Parthan
    Veena Parthan
    In computational fluid dynamics (CFD), meshing is a critical step for achieving reliable simulations, especially when combined with a robust solver strategy. As turbomachinery blade geometries become more intricate and design cycles shorten, traditio...
    • 4 May 2026
  • Legacy Node to Advanced Silicon: Schematic Migration in Cadence Virtuoso Studio

    Analog/Custom Design: Legacy Node to Advanced Silicon: Schematic Migration in Cadence Virtuoso Studio

    Sai Darshan S N
    Sai Darshan S N

    In today’s fast-paced semiconductor industry, technology nodes evolve quickly—yet analog designs often have long, productive lives. A carefully tuned amplifier, data converter, or IP block can often be reused across multiple process nodes and even across different foundries. This is where  schematic migration becomes essential. Schematic migration is now a crucial strategy for modern analog design reuse. 

    Schematic…

    • 4 May 2026
  • Unraveling Precision Time Measurement (PTM)

    Verification: Unraveling Precision Time Measurement (PTM)

    Igor Krause
    Igor Krause
    Introduction

    Precision Time Measurement (PTM) is an optional capability for communicating precise timing information between components. PTM enables precise coordination of events across multiple components with independent local time clocks. Such precise coordination is difficult, given that individual time clocks have differing notions of the value and rate of change of time. PTM is used in links/domains where the system…

    • 1 May 2026
  • 初期検討から最終最適化までのRF設計の高速化

    カスタムIC/ミックスシグナル: 初期検討から最終最適化までのRF設計の高速化

    Custom IC Japan
    Custom IC Japan
    村田製作所は、Virtuoso Studio RF向けチューニングおよび最適化ライブラリをリリースしました。 RFおよびマイクロ波システムは、5G/6G、自動車レーダー、Wi‑Fi、IoTアプリケーションの普及により、より高い周波数帯へと移行し、かつ高密度に集積されたモジュール構成が求められるようになっています。その結果、設計の複雑さはこれまでにないスピードで増大しています。初回設計での成功(ファーストパスサクセス)を達成するためには、回路トポロジそのものだけでなく、実際の部品が持つ現実的な特性...
    • 30 Apr 2026
  • New Spectre AMS Designer Features in XCELIUM 26.03

    Analog/Custom Design: New Spectre AMS Designer Features in XCELIUM 26.03

    AMSDReleaseTeam
    AMSDReleaseTeam
    The Spectre AMS Designer features are now available through the XCELIUM 26.03 release for download at Cadence Downloads. For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy.
    • 27 Apr 2026
  • Mastering Library Development in Allegro X System Capture

    System, PCB, & Package Design : Mastering Library Development in Allegro X System Capture

    Priyadarshini N D
    Priyadarshini N D

    Modern schematic-driven design flows rely on accurate, reusable, and well-structured libraries to ensure design correctness, consistency, and smooth downstream PCB implementation. In Cadence's Allegro X System Capture, library development forms the foundation of an efficient design process, enabling seamless schematic creation, constraint application, and PCB implementation.

    Join us for this free Cadence technical…

    • 27 Apr 2026
  • Accurate S-Parameter Simulations Using Spectre Simulator in Virtuoso Studio

    Analog/Custom Design: Accurate S-Parameter Simulations Using Spectre Simulator in Virtuoso Studio

    Pratul Nijhawan
    Pratul Nijhawan
    Introduction: Designing Beyond DC and Time Domain Limits

    Imagine validating high-speed interconnect or RF block operating in the multi-GHz range. Traditional modeling and simulation approaches quickly reach their limits when used to validate high speed interconnect or RF blocks operating in the multi-GHz range. When signals begin to propagate like waves, ringing and reflection dominate behavior and frequency-dependent…

    • 27 Apr 2026
  • Debugging RAVEL Rules: From Silent Failures to Visual Proof

    System, PCB, & Package Design : Debugging RAVEL Rules: From Silent Failures to Visual Proof

    ACat299612
    ACat299612
    Debugging a RAVEL rule can be deceptively difficult. A rule may run without errors, complete successfully, and yet quietly return empty relations or worse, incorrect results. Without debugging cues or a stack trace, these silent failures can stall pr...
    • 26 Apr 2026
  • Unlocking High-Speed Serial Link Signal Integrity with AMI Model

    System, PCB, & Package Design : Unlocking High-Speed Serial Link Signal Integrity with AMI Model

    Priyadarshini N D
    Priyadarshini N D
    As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often su...
    • 24 Apr 2026
  • Virtuoso Studio: Layout Editor Productivity Enhancements Blog Series: Part 1

    Analog/Custom Design: Virtuoso Studio: Layout Editor Productivity Enhancements Blog Series: Part 1

    Rohini Garg
    Rohini Garg
    Discover how new Group Array enhancements in Virtuoso Studio IC25.1 streamline editing, boost layout productivity, and simplify managing repeated structures.
    • 24 Apr 2026
  • Unraveling Embedded Clock Mode in MIPI D-PHY: Simplifying High-Speed Serial Link

    Verification: Unraveling Embedded Clock Mode in MIPI D-PHY: Simplifying High-Speed Serial Link

    ArupC
    ArupC
    As flagship smartphones push camera sensors beyond 200 megapixels and display resolutions beyond 4K, and as automotive applications demand ever-higher bandwidth, the physical layer interfaces connecting these components must evolve in lockstep. The M...
    • 23 Apr 2026
  • Struggling to Rewrite Functionality in PSS? Import Functions Streamlines

    Verification: Struggling to Rewrite Functionality in PSS? Import Functions Streamlines

    Siddh Virani
    Siddh Virani

    One of the most powerful features of the Portable Stimulus Standard (PSS) is the ability to import functions from foreign languages like C or SystemVerilog. This capability is far more than a convenience; it solves a critical real-world challenge. A very common real-life use case is that many teams already have a substantial firmware/software API library (usually in C, sometimes SV), and they do not want to re-model that…

    • 23 Apr 2026
  • エージェント型AI「Cadence AI Super Agents」が再定義する、仕様策定からサインオフまでのチップ設計

    Cadence Japan: エージェント型AI「Cadence AI Super Agents」が再定義する、仕様策定からサインオフまでのチップ設計

    Cadence Japan
    Cadence Japan
    ケイデンスは「CadenceLIVE Silicon Valley 2026」において、完全自律型チップ設計に向けたエンドツーエンドの設計フロー実現の一環として、アナログ設計・検証向けに「ViraStack AI Super Agent」、デジタル実装およびサインオフ向けに「InnoStack AI Super Agent」を新たに発表し、すでに提供しているデジタルRTL設計・検証向け「ChipStack AI Super Agent」とあわせ、チップ設計全域をカバーする自律...
    • 22 Apr 2026
  • Voices Goes to APJ: Connecting Early Career Talent and the Future of Innovation

    Life at Cadence: Voices Goes to APJ: Connecting Early Career Talent and the Future of Innovation

    Ryan Robello
    Ryan Robello
    Written by Maggie Chen Cadence wrapped up some phenomenal Voices events across Asia Pacific and Japan, geared toward early-career employees who are working at an initial level or are within two years of their most recent graduation date. A global ser...
    • 22 Apr 2026
  • Accelerating RF Design from Early Exploration to Final Optimization

    RF Engineering: Accelerating RF Design from Early Exploration to Final Optimization

    StandingWaves
    StandingWaves
    Murata Releases Tuning and Optimization Library for Virtuoso Studio RF As RF and microwave systems move to higher frequencies and densely packed modules—driven by 5G/6G, automotive radar, Wi‑Fi, and IoT applications—design complexity is i...
    • 22 Apr 2026
  • Sigrity and Systems Analysis 2025.1 HF2 Release Now Available

    System, PCB, & Package Design : Sigrity and Systems Analysis 2025.1 HF2 Release Now Available

    SigrityReleaseTeam
    SigrityReleaseTeam
    The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2025.1 HF2 release is now available for download at Cadence Downloads. This blog contains important links for accessing this release and introduces some of the main features that you can look forward to.
    • 22 Apr 2026
  • Virtuoso Studio IC25.1 ISR5 Now Available

    Analog/Custom Design: Virtuoso Studio IC25.1 ISR5 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    Virtuoso Studio IC25.1 ISR5 production release is now available for download.
    • 22 Apr 2026
  • From the Frontlines of Agentic AI EDA: Accelerated by the Arm Computing Era

    Corporate News: From the Frontlines of Agentic AI EDA: Accelerated by the Arm Computing Era

    ShrutiAnand
    ShrutiAnand
    A Report from CadenceLIVE Silicon Valley 2026 CadenceLIVE Silicon Valley 2026 opened with a high‑signal punch: a keynote fireside chat between Cadence CEO Anirudh Devgan and NVIDIA® CEO Jensen Huang, followed immediately by Devgan's visionary...
    • 21 Apr 2026
  • CadenceLIVE Wrap-Up: Where AI, Chiplets, and System Design Converged

    Corporate News: CadenceLIVE Wrap-Up: Where AI, Chiplets, and System Design Converged

    Veena Parthan
    Veena Parthan
    CadenceLIVE Silicon Valley 2026 has come to a close. What unfolded over the course of the event was a focused exploration of where semiconductor design is headed—one shaped by AI-driven workflows, advanced packaging, and system-level...
    • 17 Apr 2026
  • Day 2 in Motion at CadenceLIVE 2026: From AI Acceleration to System Realization

    Corporate News: Day 2 in Motion at CadenceLIVE 2026: From AI Acceleration to System Realization

    Reela Samuel
    Reela Samuel
    Day 2 at CadenceLIVE Silicon Valley 2026 carried a different kind of momentum. If day 1 established the architectural shift, day 2 made it operational. Across morning and afternoon tracks, the conversation moved decisively from capability to deploym...
    • 16 Apr 2026
  • Virtuoso Studio: Excellent XL- Layout XL Tools for Faster LVS Closure

    Analog/Custom Design: Virtuoso Studio: Excellent XL- Layout XL Tools for Faster LVS Closure

    Sucharita
    Sucharita
    Ensure your layout perfectly matches the schematic. Click here to discover how the latest Layout XL tools simplify LVS verification and help you achieve faster closure.
    • 16 Apr 2026
  • Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents

    Artificial Intelligence (AI): Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents

    Corporate
    Corporate
    At CadenceLIVE Silicon Valley 2026, Cadence took a major step toward fully autonomous chip design—introducing two powerful new AI Super Agents that complete an end-to-end chip design flow. The ViraStack AI Super Agent targets analog design and ...
    • 16 Apr 2026
  • CadenceLIVE Silicon Valley 2026

    Corporate News: What to Expect on Day 2 of CadenceLIVE Silicon Valley 2026

    Vinod Khera
    Vinod Khera
    If you’re searching for where semiconductor design is headed next, day 2 of CadenceLIVE Silicon Valley 2026 offers definitive insights into the future of semiconductor design. Building on day 1's strategic momentum, it explores the technol...
    • 16 Apr 2026
  • Expert Perspectives from Across the Physical AI Ecosystem

    Corporate News: Expert Perspectives from Across the Physical AI Ecosystem

    Corporate
    Corporate
    One of the most thought-provoking discussions at CadenceLIVE centered on a challenge that sits at the heart of modern system innovation—how do we ensure that what works perfectly in simulation performs just as reliably in the real world? The p...
    • 15 Apr 2026
  • Advancing Design Productivity Through AI and Super Agents

    Corporate News: Advancing Design Productivity Through AI and Super Agents

    Corporate
    Corporate
    A Defining Moment for the Semiconductor Industry Paul’s agentic AI special address opened with a clear articulation of scale and urgency: the semiconductor industry is entering a structurally different phase of growth, driven primarily by AI i...
    • 15 Apr 2026
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