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Let's be real: designing ambitious new RISC-V chips is cool, but testing them is an absolute nightmare. When you are building crazy complex pipelines and custom instructions, you eventually hit a massive brick wall. Your designs are brilliant, but traditional simulators are too slow to run actual software on them. To catch every glitch before making the physical chip,…

As designs move to advanced nodes, interconnect reliability is pushed to its limits. Narrower metal widths, higher current densities, and dense routing significantly increase exposure to electromigration (EM)—a failure mechanism that can unexpectedly undermine long‑term chip performance and reliability. When these issues surface late, the cost is paid in rework due to increasing wire widths, via insertions, which…

If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor.

At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners.

Every new SoC tape-out demands broader coverage for design robustness…

At the recent PCI‑SIG Developers Conference US held on May 6-7,2026, Cadence announced the availability of its PCIe 8.0 Verification IP (VIP)—taking another significant step in enabling early, confident adoption of the PCI Express roadmap. 

As PCIe continues to evolve to meet the growing demands of AI accelerators, high‑performance computing, and hyperscale data centers, the complexity of verification grows alongside bandwidth…

Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment. That’s because a compliance traffic generator isn’t designed to replicate real-world operating conditions, such as thermal stress, electrical noise, and the kind of bursty inference traffic that arises from…

As data rates continue to scale into the multi-tens of gigabits per second, the tolerance for uncertainty in interconnect behavior has significantly diminished. At the same time, packaging and board-level technologies are evolving toward higher density, heterogeneous integration, and greater compliance with standards. These trends have driven widespread adoption of meshed reference planes, including cross-hatch ground…

As AI systems continue to scale, adding more compute is no longer the biggest challenge. Moving enormous volumes of data between accelerators quickly, predictably, and securely is where the real complexity lies.

Scale-up interconnects have become the backbone of modern AI architectures. They must deliver ultra-low latency, massive bandwidth, and seamless interoperability—while also protecting highly sensitive data in…

The Cadence VLAB team will be part of the Cadence team present at the MATLAB Expo Japan on May 26 in Tokyo. We will be demonstrating how MATLAB and Simulink models can be used to co-simulate with VLAB virtual development machines (VDMs), allowing software to be tested in a virtual hardware-in-the-loop environment.

Virtualized hardware-in-the-loop (HIL), processor-in-the-loop (PIL), and software-in-the-loop (SIL) techniques…

AI factories are scaling rapidly. Training large models and delivering low‑latency inference now requires thousands of GPUs, accelerators, memory devices, and I/O endpoints. System efficiency increasingly depends on how data moves across the infrastructure, not compute power alone.

PCI Express^® (PCIe^®) has long been the interconnect standard for scale‑up systems, connecting CPUs, GPUs, NICs, and memory within…