Community

Address Translation Services (ATS) is one of the toughest verification problems to solve as it is the fast lane for PCIe memory access, cutting delays by caching address translations directly on the device. It keeps software behavior consistent across both PCIe Devices and RC Integrated Endpoints, making performance gains simple to adopt.

1. Translation Agent (TA):
   • Central entity, which is…

Ethernet has evolved significantly from 10 Mbps shared media to today’s multi-hundred gigabit high-speed links. One foundational feature that has enabled this scalability and ease of deployment is Auto-Negotiation (AN). Defined in multiple IEEE 802.3 clauses, Auto-Negotiation allows two connected devices to automatically determine the best possible operating parameters for a link, eliminating manual configuration…

DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety of applications, with the huge server and data center market being the key driver behind the adoption of DDR5-based memory systems. As systems move towards more CPU cores, bandwidth, and capacity, DDR5 is considered the most…

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's flagship TimeVision timing constraints management solution is now part of the Cadence portfolio, strengthening our mission to deliver the most complete and scalable timing signoff solution available on the market.

As designs push deeper into advanced process nodes, timing…

Let's be honest.

As engineers—especially in VLSI physical design—we are exceptionally good at figuring out how to do things.

Need to place macros? Done.
Route critical nets? No problem.
Insert fillers, EndCaps, DCaps? We've got scripts, flows, and muscle memory for all of it.

But here's the uncomfortable question: Do we still remember why we're doing any of this?

Somewhere between tapeout deadlines…

Cadence has reached an important milestone in its collaboration with Intel Foundry with the successful completion of its first test chips on Intel 18A earlier this year. This achievement marks a meaningful step forward in enabling advanced, standards‑based interface IP on Intel 18A. More details about these test chips were recently shared in presentations at CadenceLIVE Silicon Valley and GOMACTech events.

As system architectures…

The increasing complexity and computational demands of 3DHI systems design are challenging. On-package chiplets demand significant simulation and increasing design turns, as more designs are packaging multiple components, which only a few years ago were discretely packaged. The disparate and deep skillsets of these technologies and the exponentially increasing computational demands of newer process nodes threaten to lengthen…