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Latest Blog Posts

  • Beyond the Keynotes: Where Innovation Took a Tangible Form

    Corporate News: Beyond the Keynotes: Where Innovation Took a Tangible Form

    Veena Parthan
    Veena Parthan
    On Day 1 of CadenceLIVE 2026, the real depth of innovation unfolded on the exhibition floor—where conversations became more candid, demos more immersive, and learning far more hands-on. Customer Booths: Where Theory Met Deployment The&nbsp...
    • 15 Apr 2026
  • Key Takeaways from CadenceLIVE Silicon Valley Keynotes

    Corporate News: Key Takeaways from CadenceLIVE Silicon Valley Keynotes

    Corporate
    Corporate
    CadenceLIVE Silicon Valley opened against the backdrop of an industry under rapid transformation, where AI is no longer a downstream application but a core driver of semiconductor scale, complexity, and opportunity. Across design, infrastructure, an...
    • 15 Apr 2026
  • Why Restructuring Matters: Essential Insights for Digital Design Engineers

    Digital Design: Why Restructuring Matters: Essential Insights for Digital Design Engineers

    Udaya Shankar
    Udaya Shankar

    In the fast-evolving world of digital design, engineers are constantly challenged to deliver chips and systems that are not only functional but also optimized for power, performance, and area (PPA). Techniques such as RTL Restructuring, Logic Restructuring, and Physical Restructuring are game changers in this pursuit. Here’s why every digital design engineer should understand and leverage these methods.

    RTL Restructuring…
    • 15 Apr 2026
  • Physics Underpinning Decisions: Simulation‑Trained AI Optimizes Tokens per Watt

    Data Center: Physics Underpinning Decisions: Simulation‑Trained AI Optimizes Tokens per Watt

    Corporate
    Corporate
    The rapid rise of AI factories is pushing data center infrastructure beyond the limits of traditional planning. Rack densities have increased by an order of magnitude, liquid cooling is becoming standard, and AI workloads no longer behave predictabl...
    • 15 Apr 2026
  • The Stage Is Set: Design for AI, AI for Design at CadenceLIVE Silicon Valley

    Corporate News: The Stage Is Set: Design for AI, AI for Design at CadenceLIVE Silicon Valley

    Reela Samuel
    Reela Samuel
    Something is shifting in the world of silicon design, and you can feel it even before the first keynote begins. It is visible in early conversations around architecture choices and tool flows, in last-minute slide reviews focused on data, not positi...
    • 15 Apr 2026
  • Accelerating Semiconductor Innovation at Cloud Scale

    Cloud: Accelerating Semiconductor Innovation at Cloud Scale

    Mahesh Turaga
    Mahesh Turaga
    How Cadence Managed Cloud Services on AWS enable faster, scalable, more secure design The semiconductor industry is under unprecedented pressure. Design complexity continues to rise, schedules are tightening, and engineering resources must deliver mo...
    • 14 Apr 2026
  • C-PHYv3.0 Verification, 35% Throughput Boost for Camera and Display Designs

    Verification: C-PHYv3.0 Verification, 35% Throughput Boost for Camera and Display Designs

    Meet S Chauhan
    Meet S Chauhan

    With the evolution of advanced camera systems and higher-resolution displays for mobile devices, the challenges for MIPI (Mobile Industry Processor Interface) based systems are increasing for physical interfaces to operate efficiently over bandwidth-limited channels while supporting higher data rates, reliable signal integrity, lower power, and EMI sensitivity, along with minimal verification complexity. MIPI CPHY solution…

    • 13 Apr 2026
  • 電子回路とフォトニック回路シミュレーションの統合

    Cadence Japan: 電子回路とフォトニック回路シミュレーションの統合

    Cadence Japan
    Cadence Japan
    フォトニクスの重要性人工知能(AI)の急速な普及や高速モバイルネットワークの展開を背景に、データストレージ需要は大きく拡大しており、大量のデータを処理・転送する能力がこれまで以上に求められています。設計者は高まる帯域の要求に応えるためハードウェアの性能を限界まで引き出そうとしていますが、従来の電子回路のみのソリューションは物理的な限界に直面しています。特に、ハードウェアの消費電力や発熱は、システム性能および運用コストに対する重大な制約となっており、電力制約を超えることなく、より高速にデータを伝送...
    • 13 Apr 2026
  • Industry’s First UALink-200G Controller and PHY Running in 3nm!

    Data Center: Industry’s First UALink-200G Controller and PHY Running in 3nm!

    HW202512191014
    HW202512191014
    AI systems are running into a familiar problem. Compute keeps scaling, but the infrastructure connecting that compute is starting to dominate system behavior. Interconnect latency, bandwidth efficiency, and power now have as much impact on performanc...
    • 13 Apr 2026
  • Quantus Assistant helps users ask questions, get answers, and accelerate RC extraction workflows.

    Analog/Custom Design: Quantus Assistant: Your AI Copilot for RC Extraction

    JentilTom
    JentilTom
    An AI-powered copilot for Quantus that answers RC extraction questions in plain language, speeds learning, and helps sign-off extraction faster with confidence.
    • 11 Apr 2026
  • Scale Up vs. Scale Out in Modern AI Factories

    Data Center: Scale Up vs. Scale Out in Modern AI Factories

    HW202512191014
    HW202512191014
    Choosing pod fabrics, planning bisection bandwidth, and managing ordering semantics Two Worlds Inside the AI Factory As AI factories scale into tens of thousands of accelerators, architects must navigate two very different networking worlds. Inside a...
    • 10 Apr 2026
  • CES 2026 回顾:基于真实可用的 eUSB2V2 系统演示 筑牢信任基石

    中文技术专区: CES 2026 回顾:基于真实可用的 eUSB2V2 系统演示 筑牢信任基石

    Yaoyao Wang
    Yaoyao Wang
    没有什么比一套真实可用的系统更能建立信任。 这正是我们在拉斯维加斯 CES 2026 展会上展示的核心理念 —— 我们成功演示了业内首创的 3nm eUSB2V2 PHY IP,并与 eUSB2V2 控制器 IP在完整的端到端系统中协同运行。最终实现了实时、真实场景下的 eUSB2V2 数据通路,传输速率高达 4.8 Gbps,充分展现了这一全新 USB 接口协议的广阔前景。 本次演示的重要意义 当一项全新的接口技术问世时,技术规格与仿真验证仅仅是开始。客户与合作伙伴真...
    • 9 Apr 2026
  • Setting New Windsurfing Record Speeds Above 100 KPH With Fidelity CFD

    Computational Fluid Dynamics: Setting New Windsurfing Record Speeds Above 100 KPH With Fidelity CFD

    Veena Parthan
    Veena Parthan
    The Zephir Project, a high-performance research program led with ALTEN, was initiated to explore h, aiming to push the absolute limits of sailing speed using Fidelity CFD Software.
    • 8 Apr 2026
  • SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

    SoC and IP: SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

    Frank Ferro
    Frank Ferro
    Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability. The latest CPUs used in AI factories r...
    • 8 Apr 2026
  • 東レの3Dプリンタ用樹脂粉末データを「Digimat」材料データベースに追加

    Cadence Japan: 東レの3Dプリンタ用樹脂粉末データを「Digimat」材料データベースに追加

    Cadence Japan
    Cadence Japan
    3Dプリンタ造形における軽量化と高強度を両立する設計を支援 エムエスシーソフトウェア株式会社 (本社:東京都千代田区、代表取締役社長:今野ソックス真生、ケイデンスグループ、以下エムエスシー)は、複合材料モデリングプラットフォーム「Digimat」の材料データベース「Digimat-MX」に、東レ株式会社(東京都中央区、代表取締役社長:大矢光雄、以下「東レ」)の3Dプリンタ用樹脂粉末「トレミル®PPS」の強度解析用データを追加しました。これにより、「Digimat」ユーザーは、東...
    • 8 Apr 2026
  • CadenceLIVE Silicon Valley 2026: Powering AI, Transforming Design

    Corporate News: CadenceLIVE Silicon Valley 2026: Powering AI, Transforming Design

    Corporate
    Corporate
    Discover the future of electronics and system design at CadenceLIVE Silicon Valley 2026—a hub for bold ideas, innovative technology, and networking with the brightest minds in the industry. Mark your calendars for April 15-16, 2026, at the San...
    • 8 Apr 2026
  • EUSB2 V2 Explained: Multi Gigabit Symmetric and Asymmetric Operation

    Verification: EUSB2 V2 Explained: Multi Gigabit Symmetric and Asymmetric Operation

    WilsonKobalkar
    WilsonKobalkar
    eUSB2‑V2 is stepping into the spotlight at a time when hardware designers are being asked to do something that sounds simple but deliver more performance, in less space, with lower power, and without compromising reliability. eUSB2‑V2 represents a major evolutionary step for the USB 2.0 ecosystem.  In this blog, we’ll break down what’s new in eUSB2‑V2, how it achieves multi‑gigabit HSx operation, and why symmetric/asymmetric…
    • 8 Apr 2026
  • Cadenceが「Where You Work Matters」でプラチナ認定雇用主に選出

    Cadence Japan: Cadenceが「Where You Work Matters」でプラチナ認定雇用主に選出

    Cadence Japan
    Cadence Japan
    Cadenceは、2026年の「Where You Work Matters」リストでプラチナ認定雇用主に選出されました。本評価は、質の高い仕事を創出や従業員の成長機会を広げる取り組みが高く評価されたものです。私たちにとって最も重要な資産は人材であり、従業員の成長への取り組みが評価されたことを大変光栄に思います。米国のAmerican Opportunity Indexが運営する「Where You Work Matters」は、米国企業を対象に、従業員のキャリア成長支援、業界トップクラスの給与...
    • 6 Apr 2026
  • Training Webinar Series: Boost Design Productivity with Cadence Digital Tools

    Digital Design: Training Webinar Series: Boost Design Productivity with Cadence Digital Tools

    sakshin
    sakshin
    Stay tuned to this webinar series that helps designers explore Cadence’s latest Digital Design and Signoff tools, discover powerful debugging workflows, smart scripting techniques, rapid editing capabilities, and advanced analysis features to help you work faster and elevate your design’s PPA.
    • 6 Apr 2026
  • BETA CAE 2025.1HF2 Software Release Available

    Physical Systems Simulation (CAE): BETA CAE 2025.1HF2 Software Release Available

    Cadence BETA CAE Software
    Cadence BETA CAE Software
    Cadence BETA CAE released its 2nd Hot Fix of 2025.1 for ANSA, EPILYSIS, META, FATIQ and KOMVOS with critical bug fixes and selected implementations. Known Issues Resolved in ANSA CAD to ANSA Translators CAD to ANSA might fail for parts that contai...
    • 6 Apr 2026
  • Stop Chasing IR Drop at Signoff: See It Early, Fix It Once

    Digital Design: Stop Chasing IR Drop at Signoff: See It Early, Fix It Once

    sakshin
    sakshin
    Early Rail Analysis (ERA) is a shift‑left power integrity methodology that exposes structural power‑grid weaknesses and IR‑drop trends before full routing and signoff. It is done while the design is still malleable, reducing late‑stage ECO churn and signoff risk, especially at advanced nodes with tight voltage and EM margins.
    • 5 Apr 2026
  • Can AI + EDA Really Fix IR Drop? Inside the Voltus InsightAI Training Course

    Digital Design: Can AI + EDA Really Fix IR Drop? Inside the Voltus InsightAI Training Course

    sakshin
    sakshin
    This blog provides an in-depth look at Voltus InsightAI, Cadence’s generative AI technology, that enables customers to resolve up to 95% of violations ahead of signoff, delivering over 2× productivity improvements in EM‑IR closure.
    • 5 Apr 2026
  • 株式会社ベリフォアが日本ケイデンス・デザイン・システムズ社に統合されました

    Cadence Japan: 株式会社ベリフォアが日本ケイデンス・デザイン・システムズ社に統合されました

    Cadence Japan
    Cadence Japan
    このたび、2026年4月1日付で株式会社ベリフォアは、日本ケイデンス・デザイン・システムズ社へ正式に統合されました。 ベリフォアは、半導体設計の検証分野で高い技術力を持ち、多くの企業を支えてきた専門チームです。今回の統合により、その経験とノウハウがケイデンスのソリューションと融合し、より強力なサービス提供が可能になります。今後は、ケイデンスのグローバル技術とベリフォアの日本市場での専門性を活かし、より高品質な検証サービスを提供してまいります。引き続きお客様の課題解決と価値創出に貢献すべ...
    • 5 Apr 2026
  • One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

    SoC and IP: One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

    Joe C
    Joe C

    From smart cameras to autonomous vehicles and compact edge servers, edge AI is pushing more compute, storage, and connectivity into smaller, more power-constrained systems deployed outside the data center. These designs must simultaneously ingest sensor data, move information to local accelerators, connect to displays or storage, and maintain reliable network links—all within tight area, thermal, and BOM limits. As a…

    • 3 Apr 2026
  • Cadence@GTC 2026

    Corporate News: Cadence at NVIDIA GTC 2026: From AI Factories to Molecular Discovery

    Corporate
    Corporate
    At NVIDIA GTC 2026, the industry conversation continued its shift beyond incremental advances in chip design toward something more systemic—how complex AI-driven systems are engineered end to end. Within that context, Cadence presented a clear ...
    • 3 Apr 2026
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