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As chip designs grow larger and more complex, they become increasingly difficult to manufacture as a single piece of silicon. Yields (the percentage of properly functioning chips from a semiconductor wafer) decrease significantly with larger die sizes. This limitation of the monolithic chips led to the advent of the multi-die architecture in which the smaller dies (which are easier to produce, resulting in higher yields…

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center use cases, high-throughput die-to-die connectivity is more essential than ever. Cadence has already demonstrated its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology. To bring even greater flexibility to our mutual customers, Cadence announces that it has taped out its IP subsystem for the 32G UCIe advanced…

A new Cadence success story details how Advanced Layout Solutions (ALS), a UK-based design bureau specializing in high-speed PCBs, developed an efficient workflow that overcame significant design challenges due to increasing complexity in their projects that required higher accuracy and faster design cycles. The company’s expertise spans a range of complex designs in industries where precision and innovation are vital…

AI is driving a new semiconductor renaissance—it's no longer just a workload, but the defining force behind a new era of semiconductor innovation. Cadence Fellow Charles Alpert echoed this message in his keynote, "Design for AI and AI for Design," offering insights into how AI is reshaping infrastructure and accelerating innovation. His talk set the tone for the AI Infra Summit 2025, paving the way for the Cadence Silicon…

Are you interested in learning the key steps to designing a physical layout from synthesis to signoff? Do you want to know the latest AI features in the RTL2GDSII back-end flow?

Join Cadence Training and Sai Srinivas P, Lead Education Application Engineer, for this free technical training webinar and get insights from industry experts:
RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

In this webinar…

Alphawave Semi is a global leader in high-speed connectivity and compute silicon for customers in AI, data centers, 5G wireless infrastructure, data networking, autonomous vehicles, and storage. Faced with the exponential growth of data, the company’s leading-edge technology enables data to travel faster and more reliably using less power.

In this two-minute Designed with Cadence (DWC) video, Daniel Lambalot, senior…

In the ever-evolving world of analog design, efficiency and clarity are key. With the latest enhancements in analogLib's DeepProbe instance, designers can now leverage schematic syntax and bus format support to streamline their debugging and analysis workflows. This blog explores how these features simplify the design process and improve productivity.

One of the standout…

Join Cadence Training and Education Application Engineer Architect, Neha Joshi, for this free technical Training Webinar, which will offer a detailed overview of low-power design strategies.

Low-power synthesis isn’t just an IC design flow box to be checked; it's a foundational step and a strategic necessity.

As modern SoCs become more power-sensitive, early power optimization at the synthesis stage becomes…

In the rapidly evolving landscape of digital semiconductor design and testing, the ability to accurately diagnose manufacturing defects is critical to ensuring product reliability and optimizing yield. Cadence's Diagnostics with Modus DFT Software Solution training offers a structured and comprehensive approach to fault analysis using advanced design-for-test (DFT) methodologies. This course equips engineers and test…