Community

CXL 4.0 Verification IP Now Available!

Empowering Advanced AI, HPC, and Data-Centric Workloads with Unmatched Bandwidth, Scalability, and System Flexibility

As artificial intelligence (AI), high‑performance computing (HPC), and data‑intensive workloads continue to scale, traditional system architectures are hitting fundamental limits in memory capacity, bandwidth, and efficiency. Addressing these challenges, Compute Express…

Today’s complex electronic designs, particularly in the context of high-speed interconnects, 3D-ICs, and advanced packaging, require robust electromagnetic (EM) simulation tools that balance accuracy, speed, and integration. Now available on demand, the Cadence TECHTALK, Transform Your S/PI Analysis with Clarity 3D Solver, introduces the new automated channel extraction (ACE) feature within the Clarity 3D Solv…

Just like every year, the Embedded World took place in Nürnberg in mid-March. It was a great show, and it felt busier than last year. That feeling was supported by the conference's numbers, which show 13% more visitors than in 2025!

The increase in attendance was despite another year with travel difficulties. It seems the Embedded World cannot catch a break! Last year, an airport strike on the Monday before…

Chiplet-based architectures are quickly becoming the foundation of next-generation silicon systems. While most attention goes to high-bandwidth die-to-die links and data protocols like PCIe or CXL, an equally important layer operates quietly in the background: System Manageability.

Section 8 of the Universal Chiplet Interconnect Express (UCIe) Specification introduces the manageability architecture, which defines a standardized…

In this fast‑changing digital era, every learning milestone you achieve adds a new stamp to your professional journey. But once you've gained proficiency, what's next?

Carrying certificates everywhere is like traveling with loose papers instead of a passport—possible, but hardly practical. And no, we're not taking you back to the Stone Age—there is a smarter, modern way to showcase what you know. A …

In November 2025, ChipStack officially joined Cadence. This acquisition builds on years of collaboration, integrating ChipStack's agentic AI platform with Cadence's industry-leading verification technologies. Following the acquisition of ChipStack, Cadence has announced the launch of the…

Microwave Journal and Signal Integrity Journal recently spearheaded an online panel discussing chiplets and heterogenous integration. Ken Willis, Cadence's senior application engineering group director, multiphysics system analysis, provided his take on the challenges of advanced packaging technologies such as chiplets and 3D heterogenous integration, including integration, stacking, signal integrity, and thermal concerns…

Low-power DDR SDRAM is one of the most widely used memory types in the semiconductor market today, utilized in a diverse range of applications, including mobile/handheld devices, IoT, client and server systems, automotive, virtual reality/gaming consoles, robotics, data centers, and AI applications. The LPDDR6 SDRAM, the latest generation of low-power DRAM, was first introduced in 2025. It represents a significant advancement…

I am often asked, "What is the difference between a traditional SoC die and a chiplet die?" At a high level, the answer is that a traditional SoC is designed as a standalone single-die packaged chip, while a chiplet is part of a larger system of multiple dies packaged together. This simple answer inevitably leads to a more involved answer. To facilitate a system of chiplets, each chiplet must understand how to manage…

The proliferation of artificial intelligence, the rollout of faster mobile networks, and the corresponding demand for vast data storage all require unprecedented processing power and data transfer capacity. To meet these bandwidth requirements, designers are pushing hardware to its absolute limits. However, electrical-only solutions are hitting a physical wall. Power consumption and heat generation…

Artificial intelligence (AI) is reshaping the data center. As AI workloads scale in size and complexity, traditional hyperscale designs are giving way to AI factories—purpose-built environments engineered to manufacture intelligence efficiently, reliably, and at scale.

In an AI factory, infrastructure performance is no longer measured solely by availability or power efficiency. Instead, success is defined by tokens…