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HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the artificial intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like data centers, autonomous driving systems, servers, and cloud computing, just to mention a few domains where bandwidth and performance are key requirements.

HBM started as…

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring the Interface security of devices operating within a Trusted Execution Environment (TEE). It gives a set of rules designed to prevent and mitigate security threats in devices managed by a Trusted Computing Base (TCB). The TCB, comprising software, hardware, and firmware, enforces these security rules to ensure system integrity. Acting…

Innovative Solutions for Power-Efficient RTL Design and Technology

As semiconductor designs scale in complexity and power budgets tighten, early and accurate power analysis becomes critical. Simulation and power reduction are fundamental aspects of modern technology development. Cadence's Joules RTL Power Solution offers a comprehensive suite of tools to analyze and reduce power at the RTL level.

RTL-level power analysis…

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers.

One of the most common alternate protocols is the Compute Express Link (CXL…

The automotive industry is experiencing a significant transformation as it adopts innovations like autonomous driving technologies and ultra-connected ecosystems. At the core of this change is a rising demand for compact, high-performance semiconductor solutions that can handle the increasing complexity of modern vehicle architecture. One promising development is three-dimensional integrated circuits (3D-ICs), an innovative…

As 3D heterogeneous integration (3DHI) systems increase in complexity, the importance of the Universal Chiplet Interconnect Express (UCIe) standard is becoming critical to the future of advanced packaging and semiconductor system designs that support AI and high-power computing (HPC) applications.

A Cadence webinar featuring Sigrity Signal and Power Integrity offers a comprehensive guide for developing a functional UCIe…

The rise of chiplets in advanced system design presents opportunities as well as challenges, particularly in managing power tradeoffs. Unlike traditional system-on-chip (SoC) designs, chiplets involve complex power delivery due to their multi-die structure.

Read more to learn about power tradeoffs for chiplets and how you can go from managing early-stage power models to ensuring power integrity across interconnected dies…

In the rapidly advancing field of artificial intelligence, two neural network architectures have become prominent: convolutional neural networks (CNNs) and transformers. Each architecture has brought significant advancements to various domains, ranging from image recognition, video surveillance to natural language processing (NLP), speech recognition and generation, multimodal AI and more. This article aims to compare…