Community

The tremendous growth in large language model (LLM) size corresponds with an equally dramatic rise in agentic AI applications, which are being adopted rapidly across both enterprise and consumer markets. To accommodate this demand, hyperscale providers are deploying next-generation data centers at an unprecedented rate and scale. Each of these data centers hosts millions of AI accelerators to run agentic AI workloads…

In the chiplet marketplace, the vision of a library of chiplets that can be mixed and matched requires interoperability between chiplets (sometimes from different sources), meaning standardization is essential. By establishing common chiplet system standards, designers will be able to seamlessly integrate chiplets from different vendors, reducing development time and costs while continuing to drive innovation. Interoperability…

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle. Cadence UALink VIP supports various topologies to verify UPLI layer…

With the rapidly increasing connectivity demands driven by AI/ML and HPC/datacenter use cases, high-throughput die-to-die connectivity is more essential than ever. Cadence has been at the forefront of die-to-die connectivity solutions since 2018. In keeping with a rapidly broadening portfolio of die-to-die connectivity solutions, Cadence has taped out its IP subsystem for 32GT/s UCIe solution on Samsung's 4nm (SF4X) process…

The VLAB team at Cadence is participating in the 11th Automotive Software Frontier 2026 (ASF 2026) Online event, organized by Impress in cooperation with the Global Research Institute for Mobility in Society Institutes of Innovation for Future Society, Nagoya University, Japan. It is an online-only event that runs from February 4 to March 18, 2026 (free with registration).

The ASF 2026 explores the latest technological…

Nothing builds trust like a real working system.

That was the guiding principle behind our CES 2026 showcase in Las Vegas—where we successfully demonstrated what we believe is an industry-first 3nm eUSB2V2 PHY IP alongside eUSB2V2 controller IPs (both host and device) running together in a complete, end-to-end system. The result: a live, real-world eUSB2V2 data path performing at speeds of up to 4.8 Gbps, highlighting…

You don't walk into a modern design flow. You step inside it… and immediately realize it's a maze.

At first, everything feels reassuringly familiar. The tools behave. The objectives are clear. You're aiming for clean constraints, stable reports, and that glorious moment called signoff. Easy, right?

Then the turns begin.

One constraint tightens. A report suddenly looks different. You fix one issue…