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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

• 7 min read
AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS

Verification

System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went…

• 4 min read
ESL Market , Nufront , Altair , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Sigma , Acceleration , Functional Verification , LeCroy , Dynamic Power Analysis , Doulog , System Design and Verification , Freescale , Methods2Business , System Development Suite , Samsung , embedded software , Rohde & Schwarz , Ericsson , LSI , Palladium XP , Emulation , CSR , CDNLive! , ST Microelectronics , Texas Instruments , xilinx , DAC 2012 , ARM , Schirrmeister , Accelerated Verification IP , low power optimization

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2

Greetings, Simulating crystal oscillators got a lot easier in MMSIM12.1... We…

• 5 min read
RF , RF Simulation , analog/RF , APS , Circuit simulation , Virtuoso Spectre , HB , Spectre RF , Analog Simulation , MMSIM , Virtuoso Spectre Simulator GXL , MMSIM 12.1 , analog , Analysis , ADE , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , VCO , crystal oscillator , Oscillator , simulation

System, PCB, & Package Design 

Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in…

For most IC package designers, the GDSII format is a part of daily life. You may…

• 5 min read
SiP , IC Package , IC Packaging , GDSII , packaging , cadence , Digital SiP design , stream , 16.6 , GDS-II , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , APD 16.6 , SiP Layout , Physical layout and co-design

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 1

Greetings! Simulating Crystal Oscillators got a lot easier in MMSIM12.1... We…

• 8 min read
RF , RF Simulation , analog/RF , 12.1 , HB , Spectre RF , ADE-L , Analog Simulation , MMSIM , MMSIM 12.1 , analog , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , Circuit Design , harmonic balance , VCO , crystal oscillator , Oscillator

Verification

University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level…

Today we issued a Japan-only press release announcing a high-level synthesis joint…

• 2 min read
High-Level Synthesis , university , TLM-driven design , TLM , japan , SystemC , C-to-Silicon Compiler , DAC 2012 , Aizu , C++

Verification

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with…

• 4 min read
High-Level Synthesis , Flex Channels , C-to-Silicon 12.2 , Jack Erickson , IP re-use , rtl compiler , SystemC , C-to-Silicon Compiler , HLS , clock gating , QoR , System Design and Verification

Analog/Custom Design

Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California…

• 5 min read
Static timing analysis , mixed-signal seminars , AMS , static analysis , EDI , microcontrollers , ARM Cortex M0 , mixed signal design , cadence , Functional Verification , mixed signal methodology , mixed signal solution , Open Access , STA , Verilog-AMS , timing model , FTM , Mixed-Signal , MCUs , encounter , Mixed-Signal Technology Summit , analog behavoral , analog behavioral models , analog/mixed-signal , mixed signal physical implementation open access , model validation , Signal Integrity , Virtuoso , Spectre , Cortex-M0 , oa , RNM , mixed signal methodology guide , real number types , Mixed signal physical implementation , behavioral models , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , wreal , real number models , ARM , ARM-Cortex-M , OpenAccess , SPICE , mixed signal implementation , liberty model , simulation , AMS Verification

Verification

Securing the Internet of Things

While I had looked at the challenges of hardware/software integration in various…

• 3 min read
security , Intel , device security , hackers , System Development Suite , Amphion Forum , embedded software , Green Hills , burning printer , Mocana , software security , cyber attacks , Internet of Things , phone emissions , Schirrmeister , HW/SW Co-Development

System, PCB, & Package Design 

What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over…

• 3 min read
PCB , PCB Layout and routing , RF , Allegro 16.6 , RF PCB , Routing , 16.6 routing , PCB Editor , Layout , design , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Digital Design

SPICE Correlation Made Easy by Encounter Timing System (ETS)

Hello, and welcome to my first blog! As an application engineer in customer support…

• 4 min read
app note , Static timing analysis , ets , mukesh , STA , spice correlation , Spectre , signoff , ETS create_spice_deck , Encounter Timing System , SPICE

Verification

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews

System, PCB, & Package Design 

Leverage System Planning to Maximize Performance of Silicon Interposer

Recently, an article was published in Chip Scale Review by Cadence product manager…

• 2 min read
SI , PI , Chip Scale Review , SiP , IC Packaging , Team Allegro , 3D IC , Kevin Rinebold , 3D-IC , Power Integrity , TSV , silicon interposer , Signal Integrity , 2.5D IC , system planning , system co-analysis , 2.5D

System, PCB, & Package Design 

What's Good About RF SiP and Data Management? Look to 16.6 and See!

The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity…

• 2 min read
PCB , IC Packaging and SiP Design , Allegro RF SiP , SiP , IC Packaging , Allegro 16.6 , die abstracts , RF SiP , IC/package co-design , design , PCB design , Grzenia , SiP Layout , die abstract , Virtuoso SiP

System, PCB, & Package Design 

Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application…

Whether it is reducing mouse clicks, minimizing access to menus, eliminating the…

• 3 min read
package , SiP , IC Package , IC Packaging , cadence , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , Allegro Package Designer , APD 16.6 , SiP Layout , wirebonding

Analog/Custom Design

Mixed-Signal Technology Summit in Japan Provides Technology Updates

Japan’s semiconductor industry is undergoing a significant change in recent years…

• 3 min read
AMS , uvm , Virtuoso-AMS , microcontrollers , ARM Cortex M0 , mixed signal design , Mixed-Signal On Top , AMS-Designer , MS ToT , IC 6.1 , A/MS , mixed signal methodology , tech on tour , AMS Designer , analog on top , Open Access , Cortex-M , Verilog-AMS , analog , Mixed-Signal , encounter , Mixed-Signal Technology Summit , LDE , analog behavioral models , analog/mixed-signal , Virtuoso , mixed-signal book , Cortex-M0 , oa , ClioSoft , metric-driven verification , mixed signal , wreal , micro-controllers , ARM , ARM-Cortex-M , OpenAccess , Common Power Format , AMS Verification , TowerJazz , Matlab , real number

Verification

Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to T…

One of the main benefits of moving the design entry point up in abstraction from…

• 1 min read
uvm , TLM , Jack Erickson , Functional Verification , abstraction , webinar , metric-driven verification , SystemC , Watanabe , MDV , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI Setup/Audit? 16.6 has Many New Enhancements!

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release…

• 8 min read
PCB SI , PCB , SI , diff pairs , Allegro 16.6 , setup/audit , Signal Intregrity , SigXP UI , DRC , 16.6 , PCB Signal and power integrity , "PCB SI" , High Speed , PCB power integrity , diff pair , setup , differential pair , Signal Integrity , audit , design , Allegro PCB SI , PCB design , "PCB PI" , Grzenia , differential pairs , SI analysis and modeling , Differential Pair Support , power , Allegro
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