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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

• less than a min read
DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Verification

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

• 1 min read
IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Welcome to Richard Goering

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering…

• less than a min read
Industry Insights , Functional Verification , EDA

Analog/Custom Design

What’s all the Hoopla with PDKs?

At a purely technical level, Process Design Kits are fairly innocuous. They are used…

• 2 min read
IC 6.1 , Virtuoso , PDK , Custom IC Design , Process Design Kit

Analog/Custom Design

Analog Design Validation: What is Your Recipe for Success?

Every analog circuit design goes through some kind of electrical validation step…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

SoC and IP

DRAMs: Historically, how bad is this downturn?

DRAMs: Another look at how bad it is: Last week, we (finally) published our summary…

• 3 min read

Verification

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

• 2 min read
validation , embedded world conference , System Design and Verification , ISX , ARM , verification

Analog/Custom Design

Virtuoso, the SATs, and The Dark Knight - Part I

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight…

• 1 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS"…

• 5 min read
SaaS , Functional Verification , Harry The ASIC Guy , DVcon , Xuropa

Analog/Custom Design

Automated Digital Block Implementation Using Virtuoso

Have you ever found yourself laying out a digital block in Virtuoso where you have…

• 2 min read
VSR , Virtuoso Custom Placer , Virtuoso , Custom IC Design , VCP

Digital Design

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important…

Having consistency and correlation in timing analysis across the design flow is …

• less than a min read
EDN , encounter , Digital Implementation , Encounter Timing System

Verification

Is Software Engineering Engineering? You Decide!

Last night when I was waiting for my daughter to finish orchestra rehearsal (she…

• 3 min read
System Design and Verification , failure tolerance , software engineering , design metrics

Analog/Custom Design

Calculating Large Signal Phase Noise Using Transient Noise Analysis

My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group. We…

• 2 min read
PLL , MMSIM , RF design , Circuit Design , Simulators , Custom IC Design

Digital Design

Get on Board With Bus Guides

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you…

• 2 min read
Bus Guides , encounter , 8.1 , Digital Implementation

System, PCB, & Package Design 

What's Good About Cline Change Width in APD? It's in SPB16.2!

In IC package design, it is becoming increasingly necessary to change a cline’s width…

• 2 min read
SPB 16.2 , APD , PCB design , Cline change

Verification

Generation Action: Constraints From Above

[Welcome guest blogger Reuven Naveh of Specman R&D] What is the “constraints from…

• 6 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty…

• 1 min read
System Design and Verification , Palladium , incyte , C-to-Silicon Compiler

Analog/Custom Design

Moving an Ecosystem

Recently, a colleague here at Cadence created the image of an ecosystem , whose existence…

• 1 min read
ecosystem , Virtuoso , CAD , Custom IC Design

SoC and IP

Company Financials for 4Q08. Not Good

Memory Makers lose $8.8B in 4Q2008, to bring annual losses to $20B: Memory companies…

• 14 min read
CDNS - Fix Layout Hompage