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System, PCB, & Package Design 

Cadence's Acquisition of Hexagon D&E: A Game-Changer for Multiphysics Innovation

Having spent six rewarding years at Hexagon Design and Engineering (D&E), followed…

Stephen Smith
• 2 min read
Cadence Design Systems , featured , Hexagon , market leader , multiphysics

Corporate News

The New Engineering Stack: Accelerated Computing and Agentic AI

Accelerated computing is now the primary design hardware platform for engineering…

Corporate
• 3 min read
featured , GTC , NVIDIA

Life at Cadence

We're Celebrating Black History Month with Our Employees

At Cadence, we're recognizing Black History Month by celebrating our employees, amplifying…

Ryan Robello
• 3 min read
featured , LifeAtCadence

Analog/Custom Design

Virtuoso Studio IC25.1 ISR4 Now Available

Virtuoso Studio IC25.1 ISR4 production release is now available for download.

KomalJohar
• 5 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Computational Fluid Dynamics

Thermal Analysis of a Hardware Blade System

Here's a video titled Thermal Analysis of a Hardware Blade System. The "blade system…

• less than a min read
CFD , celsius , protium x1

Breakfast Bytes

Package Assembly Design Kits

At the recent IMAPS conference, Cadence's John Park presented on Package Assembly…

• 3 min read
system in package , imaps , packaging , chiplet , adk , PDK

Breakfast Bytes

Sunday Brunch Video for 25th April 2021

https://youtu.be/ZuxS3yM7RCw Made at Communication HIll, San Jose (camera/drone…

• less than a min read
sunday brunch

Verification

What Is New in the Latest AMBA 5 ACE, AXI and AHB Protocol Specification Updates…

The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further…

• 1 min read
amba5 , Functional Verification , ACE5 , AXI5 , AMBA VIP , AMBA Verification IP , AHB5

Computational Fluid Dynamics

This Week in CFD

This week’s compilation of CFD news begins with a must-read article on how to choose…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Digital Design

Pegasus: Get Your Wings: Strong Immunity Makes Pegasus Fault Tolerant

We all know the importance of good immunity and how a good immune system makes you…

• 1 min read
Pegasus Verification System , Fault Tolerance , pegasus , signoff , silicon signoff

Breakfast Bytes

Dover and Cadence: Lessons Learned from SolarWinds

I recently attended a webinar with presenters from Dover, Cadence, and a mystery…

• 6 min read
security , solarwinds , dover , Tensilica

Breakfast Bytes

Tensilica Vision Q8 and P1 DSPs, More AND Less

President George H. W. Bush famously said that he didn't do "the vision thing". Well…

• 5 min read
vision q8 , featured post , vision p1 , Tensilica , vision , neural networks

Digital Design

Low-Power Implementation Training Videos

This blog post describes the Low Power Implementation Flow and IEEE 1801 basic terminologies…

• 1 min read
Low Power , Digital Implementation , Innovus , Power Analysis

カスタムIC／ミックスシグナル

Virtuoso Video Diary: 改善されたReference Historyと新機能Merge HistoryによるIncremental Simu…

Virtuoso® ADE Assembler で以下のような状況に陥ったことはありませんか？ ・Interactiveヒストリに結果がありますが、すべてのスイープ…

• less than a min read
Analog Design Environment , ICADVM18.1 , Virtuosity , Virtuoso Video Diary , japanese blog , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Digital Design

Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protectio…

This blog discusses the different Voltus electrostatic discharge (ESD) checks in…

• 4 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Full-Chip , ESD

Analog/Custom Design

Start Your Engines: Seven Habits of Highly Efficient Mixed Signal Verification E…

This blog shares insights on the seven best practices that should be followed by…

• 8 min read
AMS-Designer , mixed-signal methodology , Start Your Engines , Virtuoso , mixed signal , AMS Verification , mixed-signal verification

Verification

PSS2.0 is Out – Reflections on the Role of a Standard

We all know that a common language is the basis for every collaborative activity…

• 3 min read
portable test and stimulus standard , standardization , pss2.0 , pss

System, PCB, & Package Design 

(P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Sear…

As a designer, your requirement at the early stages of schematic design is quite…

• 4 min read
17.4 , cadence , OrCAD Capture , PSpiceA/D , logical design , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD , Part Search , simulation , Schematic

Breakfast Bytes

Embracing a Zero Trust Security Model

A couple of months ago, the National Security Agency (NSA) published a document titled…

• 4 min read
security , nsa , zero trust

Breakfast Bytes

Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO)

I have been criticized in the past for calling OrbitIO the "red-headed stepchild…

• 6 min read
system in package , 3DIC , OrbitIO

Verification

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
SoC verification , ccix , PCIe , coherency , CXS

Verification

PSS 2.0 Is Available and Driving Portable Stimulus to the Mainstream!

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released…

• 2 min read
Perspec , pss , portable stimulus , verification

Breakfast Bytes

Update: Pointwise, PCIe, RISC-V

This is another of my occasional update posts, covering changes to recent posts that…

• 3 min read
risc-v , pcie 5 , Pointwise , PCIe
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