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Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: Mystery Behind the .simrc File and Netlist Customization

Read on to know the usefulness of the .simrc file and how and when it is picked by…

• 7 min read
ic design methodology , AMS , Analog Design Environment , ic analog design , Cadence blogs , programming , mixed-signal simulators , custom/analog , Analog Simulation , analog , Mixed-Signal , full custom ic design , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , cadenceblogs , ICADVM20.1 , Circuit Design , mixed signal , analog design , Custom IC Design , IC6.1.8 , SKILL , Schematic , Analog IC Design , custom design technology , custom integrated circuit

Breakfast Bytes

Quantum Computing with Spectre's Ultra-Low Temperature Models

Equal1 has just announced a breakthrough in quantum computing with a fully integrated…

• 6 min read
quantum computing , 22fdx , gf , GlobalFoundries , FD-SOI

PCB、IC封装：设计与仿真分析

动态电压和频率调节如何影响功耗

本文要点 降低 CPU 或 GPU 功耗的技术有许多，这些技术聚焦软件/固件层面、系统层面和晶体管架构层面 其中两种降低功耗的技术为：动态电压和频率调节，即调整电源电平…

• less than a min read
PI , Chinese blog , 电源完整性 , 仿真分析 , GPU , 功耗 , Sigrity X , 中文 , 系统分析 , Sigrity , CPU

System, PCB, & Package Design 

BoardSurfers: Training Insights: A Comprehensive Solution for Setting Up PCB Design…

PCB design complexities increase with the increase in the number of parts and layers…

• 3 min read
17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

Breakfast Bytes

New Banknote with Alan Turing: "This Is a Foretaste of What Is to Come, and the Shadow…

Today is Alan Turing's birthday. More to the point, today the first £50 banknotes…

• 5 min read
bank of england , bletchley park , computer science , turing

Digital Design

Pegasus: Get your Wings: Pegasus Run Controls

Have you ever been in a situation where the run has started and you realize that…

• 4 min read
Pegasus Verification System , Run Control Commands , pegasus , Pegasus Run Control , signoff

Computational Fluid Dynamics

Overcoming Geometry Model Challenges for CFD Mesh Generation

I have often said that geometry modeling is to mesh generation what turbulence modeling…

• 7 min read
CFD , geometry modeling , Pointwise , Computational Fluid Dynamics , CAD , Mesh Generation , Computer Aided Design

Computational Fluid Dynamics

New Release - Omnis Version 5.1 Is Out Now!

Want to see it in action? VIEW WEBINAR RECORDING The newest version of the…

• 2 min read
CFD , Computational Fluid Dynamics , Omnis

Breakfast Bytes

Jim Hogan and Ed McCluskey Named Honorees of the Phil Kaufman Hall of Fame

In February of this year, the ESD Alliance and IEEE CEDA announced the creation of…

• 4 min read
ieee ceda , Jim Hogan , jed mccluskey , esd alliance

Verification

PIPE SerDes Architecture for PCIe Gen 5 and Beyond

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification…

• 2 min read
Intel , IP verification , PHY , pcie 5 , VIP , PCIe , SerDes , pcie gen6

Computational Fluid Dynamics

This Week in CFD

It's a short week here at Cadence CFD as we celebrate the Juneteenth holiday today…

• less than a min read

PCB、IC封装：设计与仿真分析

Cadence 收购计算流体动力学公司 NUMECA

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “Cadence to Acquire Computational…

• less than a min read
CFD , Chinese blog , 计算流体动力学 , 中文 , 系统分析 , NUMECA , 多物理场仿真 , Omnis

Analog/Custom Design

Virtuosity: Bindkeys in Virtuoso Layout Suite

You can use Virtuoso keyboard shortcuts called bindkeys in Virtuoso Layout Suite…

• 3 min read
Virtuoso Layout Bindkeys , Bindkeys in VLS , Virtuoso Keyboard Hotkeys , ICADVM20.1 , Virtuoso Keyboard Shortcuts , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

The EVS Codec: The Movie

I have written before about standards in general (including one that is 2000 years…

• 2 min read

System, PCB, & Package Design 

(P)SpiceITUp: The Power of Options in Managing Accuracy and Speed Using Relative…

The tolerances are not unique to only PSpice or simulators, they are part of any…

• 5 min read
17.4 , OrCAD Capture , PSpiceA/D , logical design , (P)SpiceItUp , PSPICE , 17.4-2019 , OrCAD , simulation

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectreアナログフォルト解析の紹介

プロセスの微細化に伴い、不具合が発生しやすくなったため、チップテストの要求が厳しくなっています。これらの欠陥はフォルトとしてモデル化され、回路シミュレータに提供されてフォルト解析が行われます…

• less than a min read
onestep , fault analysis , DFA , timezero , opens , bridges , Legato Reliability Solution , maxiters , custom faults , direct fault analysis , spectre_fsrpt , faultleadtime , tfa , Spectre , spectre_ddmrpt , parametric faults , linear , japanese blog , transient fault analysis , detection matrix

Spotlight Taiwan

Allegro X 設計平台  - 下一代智慧系統設計的新革命

原文出處: Allegro X, the Design Platform for the Next Generation of Intelligent System…

• less than a min read
PCB , taiwanese blog , allegro x

Digital Design

Voltus Voice: Unleashing the Power of Intelligent System Design Strategy - A chat…

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how…

• 9 min read
Innovus Power Integrity , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , hierarchical power integrity analysis , Digital Implementation , Multiphysics System Analysis , Tempus Power Integrity

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3Dでのポート定義

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso Meets Maxwell , Electromagnetic analysis , EMX , EM Analyis , RF design , ICADVM20.1 , japanese blog , Custom IC Design , Virtuoso Layout Suite EXL
CDNS - Fix Layout Hompage