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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

RSA Wrapup: Song, Darling, Thrun

The closing session of the RSA conference was a sort of chat-show hosted by Hugh…

• 5 min read
sebastian thrun , security , artificial intelligence , rsa conference , rsa , kate darling , dawn song

Analog/Custom Design

Virtuoso Video Diary: What's this Net Connected to?

Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where…

• 1 min read
Virtuoso Schematic Editor , Virtuoso , Schematic Editor , Virtuoso Video Diary , Circuit Design , Probes assistant , Custom IC Design , Schematic

Breakfast Bytes

Why Millennial Engineers Should Work for Cadence

Many years ago, when Nokia was at the top of its game—one in every three phones shipped…

• 5 min read
andy kessler , EDA

Academic Network

Academic Track at CDNLive EMEA 2018

From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days…

• 6 min read
hololens , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Risc V , Academic Network , UC Berkeley

Verification

Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

Welcome to the first installment of a three-part blog series examining the issues…

• 2 min read
cloud-based verification , Functional Verification , cadence cloud , cloud computing

Breakfast Bytes

The Design Infrastructure Alley

One of the new things at DAC this year is the Design Infrastructure Alley. The Alley…

• 4 min read
dac55 , DAC , infrastructure alley

Breakfast Bytes

Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet…

• 3 min read
DAC , ChipEstimate.com , Perspec , pss

System, PCB, & Package Design 

What Is COM /JCOM Channel Compliance All About?

In today’s world of double-digit gigabit-per-second data rates it is imperative that…

• 3 min read
SI , JCOM , Channel Operating Margin (COM) , COM/JCOM , JCOM channel compliance , COM , Channel Operating Margin , Signal Integrity , SystemSI

Breakfast Bytes

"I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine…

• 5 min read
exponential , moore's law , baumol's cost disease

Whiteboard Wednesdays

Whiteboard Wednesdays - What Really Matters When Selecting IP

In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of…

• less than a min read
Whiteboard Wednesdays , IP , SoC Integration

Digital Design

High-Level Synthesis: The Secret Is Out

Gone is the day when companies (our customers) kept their use of high-level synthesis…

• 2 min read
High-Level Synthesis , CDNLive , Stratus , HLS

Breakfast Bytes

Imec on EUV. Are We There Yet?

I already gave an introduction to my first visit to imec in my life in my post If…

• 7 min read
imec , stochastics , EUV

Breakfast Bytes

What's For Breakfast? Video Preview June 18th to 22nd 2018

https://youtu.be/puYFl7m50tM Coming from Dilijian Armenia (camera Gary Bengier…

• less than a min read
rsa conference , rsa , Dolby , millennial , virtual cad , Tensilica , ludwigsburg , dap light

Verification

DMS 2.0 - What's Cool and What's New

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)…

• 1 min read
digital mixed signal , Functional Verification , DMS 2.0 , xcelium simulator

Breakfast Bytes

FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey

Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only…

• 3 min read
FinFET , FD-SOI

Analog/Custom Design

Virtuosity: Let's Have Fun with ADE Debugging – Part 1

Over the years, we have seen our customers’ usage of ICRPs increase dramatically…

• 9 min read
performance , ADE Explorer , ADE L , Virtuoso , ADE-XL , Virtuosity , Simulators , Custom IC Design , ICRP , ADE Assembler

Breakfast Bytes

Why Did EDA Have a Hardware Business Model?

Business models are really important. Just ask any internet startup company that…

• 7 min read
term license , hardware , EDA , cadence cloud

Analog/Custom Design

Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available

The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download…

• 3 min read
IC , ISR20 , ICADV12.3 , ADE , Layout , Virtuoso , Virtuosity , IC6.1.7 , Custom IC Design , Custom IC

Verification

Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic…

• 2 min read
SystemVerilog , uvm , Dynamic Test Load , Functional Verification , xcelium
CDNS - Fix Layout Hompage