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Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: Did My Checks Pass or Did They Not Run?

If you've ever tried to run the Checks/Asserts flow in Virtuoso ADE Assembler and…

• 2 min read
ADE Explorer , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

After Meltdown and Spectre

At the recent Linley Spring Microprocessor Conference, the second day's keynote was…

• 7 min read
meltdown , processor , Linley , Spectre

Digital Design

LIBERATE 19.2 Base Release Now Available

The LIBERATE 19.2 production release is now available for download at Cadence Downloads…

• 2 min read
Liberate AMS , Bolt Job Distribution , Liberate Release Blog , Cadence blogs , characterization , liberate trio , LIBERATE19.2 , Liberate LV , Health Incident Report , Liberate Variety , Liberate MX , Digital Implementation , Ascava Distillation , Liberate , Characterization Portfolio , Liberty , Leakage Power Management

Breakfast Bytes

Bob Smith on ESD Alliance, ES Design West...with Wine

I talked to Bob Smith recently about what's coming up in the world of the ESD Alliance…

• 4 min read
semicon , semi , es design west , esd alliance

Breakfast Bytes

Sunday Brunch Video for 12th May 2019

https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

通过人工神经网络探讨信号完整性的未来

想象一下，如果电脑或机器人可以完成所有枯燥乏味的工作，我们就能享受生活、做更多有意义的事。这些绝对是许多学术界、工业界研究人员的愿望。工程师的最终梦想是，按下一个…

• 1 min read
SI , Chinese blog , 人工神经网络 , 中文 , Sigrity , SystemSI , 信号完整性

Digital Design

HLS Optimizations You Can't Do By Hand

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable…

• 3 min read
High-Level Synthesis , Stratus , SystemC , HLS

Breakfast Bytes

150th Anniversary of the Transcontinental Railroad

150 years ago, technology meant railroads, not semiconductors. I mean, precisely…

• 4 min read
railroad

System, PCB, & Package Design 

Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

As transistor device scaling gets closer and closer to physical limits, more and…

• 2 min read
advance packaging , Silicon-interposer 2.5D package-based test , reference flow , Samsung , CDNLive 2019 , package design , DesignCon 2019 , FO-PLP , Sigrity , CDNLive San Jose , Package signoff , Advanced Package design and sign-off reference flow

Analog/Custom Design

Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

Have you ever wanted to sweep DSPF files across corners, plot terminal current and…

• 4 min read
ADE Explorer , post-layout , DSPF , Virtuoso Analog Design Environment , postlayout , Virtuosity , ADE Assembler

Breakfast Bytes

Intel at Linley

At the recent Linley Spring Microprocessor Conference, there were two presentations…

• 4 min read
Intel , Linley

Verification

Concurrent Actions in Specman: Part 2

In the previous blog: Concurrent Actions in Specman , we discussed the existing options…

• 4 min read
Specman , Specman/e , Specman e , concurrency , specman elite

Breakfast Bytes

How Do Out-of-Order Processors Work Anyway?

I've been meaning to write a post on how out-of-order processors work, but one challenge…

• 8 min read
processor , Linley , red hat , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays - Limitations of Scan Compression QoR

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital…

• less than a min read
Whiteboard Wednesdays , modus , Scan Compression

The India Circuit

A Special Day for Cadence India

A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate…

• 1 min read
One Cadence-One Team , Volunteer Time Off , Cadence India , Rise Against Hunger

Breakfast Bytes

JasperGold: the Next Generation

Formal verification has gone through a number of eras. In the early 1990s, it was…

• 3 min read
formal , machine learning , JasperGold , Formal verification , verification

Analog/Custom Design

Virtuoso Video Diary: What's New in Reliability Setup

Read this blog to know about the enhancements made to the reliability options form…

• 3 min read
Stress Analysis , Analog Design Environment , relxpert , ICADVM18.1 , ADE Explorer , MMSIM , ADE XL , ADE , ISR3 , reliability options , Virtuoso Analog Design Environment , Spectre , ADE-XL , Virtuosity , Virtuoso Video Diary , aging , reliability analysis , Custom IC Design , IC6.1.8 , reliability , ADE Assembler

Breakfast Bytes

Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red

I wrote last Friday in my post TSMC: Zero Excursion, Zero Defect about the statistical…

• 6 min read
statistical power

Digital Design

A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss …

• 1 min read
effective resistance , electromigration , clamps , electrostatic discharge , current density , differential voltage , EPS , Voltus , rule file , parallel processing , Innovus , EM , Charged Device Model , massively parallel , bump , ESD
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