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Featured

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
Corporate 28 Oct 2025 • 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Oct 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
Veena Parthan 21 Oct 2025 • 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
Corporate 21 Oct 2025 • 1 min read
featured , innovation , Beta CAE , event , AI
cdns - all_blogs_categories

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Blog - Post List

Latest blogs

Breakfast Bytes

Cadence Cloud

Today Cadence announced Cadence Cloud. This is the beginning of a major change in…

Paul McLellan 25 Jun 2018 • 7 min read
passport , cloud , cadence cloud , Hosted Design Solutions

Breakfast Bytes

Remember Virtual CAD? DesignSphere Access? What an ASP Was?

Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology…

Paul McLellan 22 Jun 2018 • 4 min read
asp , cloud , cadence cloud , esd alliance

Verification

Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

Welcome back to our series on cloud verification solutions. This is part two of a…

XTeam 21 Jun 2018 • 1 min read
uvm , Functional Verification , EDA , HPC , cadence cloud

Verification

App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog…

Welcome back to the third installment of a special multi-part edition of the App…

XTeam 21 Jun 2018 • 2 min read
SystemVerilog , Tip , Functional Verification , App Note Spotlight

Breakfast Bytes

Automobil Elektronik Kongress 2018

Once a year for 22 years the electronic divisions of the European automotive industry…

Paul McLellan 21 Jun 2018 • 6 min read
Automotive , ADAS , autonomous vehicles

Breakfast Bytes

What's For Breakfast? Video Preview June 25th to 29th 2018

https://youtu.be/-fwwmFE6yUs Coming from Automotiv Elektronik Kongress (camera…

Paul McLellan 20 Jun 2018 • less than a min read
dac55 , DAC

Breakfast Bytes

Movie Theater Sound in Your Phone

Dolby Atmos is immersive sound. As Dolby puts it: Dolby transports you into the…

Paul McLellan 20 Jun 2018 • 3 min read
hifi3 , atmos , Dolby , mwc china , Tensilica , Huawei

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to ADAS  with a Real-Life Example

In this week’s Whiteboard Wednesdays video, Marc Greenberg, walks us through a typical…

References4U 19 Jun 2018 • less than a min read
Whiteboard Wednesdays , self-driving car , ISO 26262 , ADAS

Breakfast Bytes

RSA Wrapup: Song, Darling, Thrun

The closing session of the RSA conference was a sort of chat-show hosted by Hugh…

Paul McLellan 19 Jun 2018 • 5 min read
sebastian thrun , security , artificial intelligence , rsa conference , rsa , kate darling , dawn song

Analog/Custom Design

Virtuoso Video Diary: What's this Net Connected to?

Meet the Virtuoso Schematic Editor L Probes assistant, a dockable assistant where…

sarahfino 19 Jun 2018 • 1 min read
Virtuoso Schematic Editor , Virtuoso , Schematic Editor , Virtuoso Video Diary , Circuit Design , Probes assistant , Custom IC Design , Schematic

Breakfast Bytes

Why Millennial Engineers Should Work for Cadence

Many years ago, when Nokia was at the top of its game—one in every three phones shipped…

Paul McLellan 18 Jun 2018 • 5 min read
andy kessler , EDA

Academic Network

Academic Track at CDNLive EMEA 2018

From 7-9.05 the CDNLive circus made it stop in Munich / Germany for full three days…

Anton Klotz 17 Jun 2018 • 6 min read
hololens , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Risc V , Academic Network , UC Berkeley

Verification

Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

Welcome to the first installment of a three-part blog series examining the issues…

XTeam 15 Jun 2018 • 2 min read
cloud-based verification , Functional Verification , cadence cloud , cloud computing

Breakfast Bytes

The Design Infrastructure Alley

One of the new things at DAC this year is the Design Infrastructure Alley. The Alley…

Paul McLellan 15 Jun 2018 • 4 min read
dac55 , DAC , infrastructure alley

Breakfast Bytes

Pie and Chips at DAC: ChipEstimate.com and the First Annual Pi Contest

In Scotland, there is a traditional dish of pie and chips. But the pie is not a sweet…

Paul McLellan 14 Jun 2018 • 3 min read
DAC , ChipEstimate.com , Perspec , pss

System, PCB, & Package Design 

What Is COM /JCOM Channel Compliance All About?

In today’s world of double-digit gigabit-per-second data rates it is imperative that…

Sigrity 13 Jun 2018 • 3 min read
SI , JCOM , Channel Operating Margin (COM) , COM/JCOM , JCOM channel compliance , COM , Channel Operating Margin , Signal Integrity , SystemSI

Breakfast Bytes

"I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car"

Agatha Christie, looking back on her early life, remarked that she: I couldn’t imagine…

Paul McLellan 13 Jun 2018 • 5 min read
exponential , moore's law , baumol's cost disease

Whiteboard Wednesdays

Whiteboard Wednesdays - What Really Matters When Selecting IP

In this week’s Whiteboard Wednesday, Tom Hackett says that PPA is only the tip of…

References4U 12 Jun 2018 • less than a min read
Whiteboard Wednesdays , IP , SoC Integration

Digital Design

High-Level Synthesis: The Secret Is Out

Gone is the day when companies (our customers) kept their use of high-level synthesis…

dpursley 12 Jun 2018 • 2 min read
High-Level Synthesis , CDNLive , Stratus , HLS
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