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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

Breakfast Bytes

Care for Some Gates With Your Server?

One of the big themes from the Linley Data Center Conference earlier this month was…

• 4 min read
Intel , GPU , data center , Altera , HBM , cloud , High Bandwidth Memory , Stratix , datacenter , FPGA , cloud computing

Whiteboard Wednesdays

Whiteboard Wednesdays—Ethernet and Automotive Electronics

In this week's Whiteboard Wednesdays video, Sachin Dhingra follows up on last week…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , Automotive Ethernet , automotive electronics

Breakfast Bytes

Cadence at embedded world—ADAS, the Stepping Stone to Self-Driving Cars

Cadence will be at embedded world in Nüremberg from February 23 to 26. We will be…

• 3 min read
functional safety , vision processing , nüremburg , ECU , Automotive Ethernet , Tensilica , ISO 26262 , Embedded World , video processing , audioprocessing , Breakfast Bytes

Verification

Functional Verification Closure—Are We Done Yet?

In my job as product marketing director for vManager and MDV, I get to hear this…

• 4 min read
methodology , verification strategy , Functional Verification , Metric Driven Verification , vPlan , Incisive , Plan and metrics management , vManager

Breakfast Bytes

Interface IP in Consumer Electronics

What is the consumer marketplace? It is a bit of a tautology, but it is electronic…

• 3 min read
IP , Consumer Electronics , interface IP , Breakfast Bytes

Breakfast Bytes

Software-Driven Hardware Verification

There is a transition going on in the system and semiconductor worlds. Some system…

• 4 min read
palladium z1 , virtual platform , Palladium , Emulation , software , Breakfast Bytes , verification

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Shape Edit Application Mode? New Capabilities…

The Allegro PCB Editor 16.6-2015 release provides Shape Edit Application Mode, a…

• 6 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , High Speed , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Where Ethernet Is Used in Automotive Electronics

In this week's Whiteboard Wednesdays video, Sachin Dhingra takes a closer look at…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , Automotive Ethernet , Ethernet

Breakfast Bytes

Where You Going? Barcelona (and Mobile World Congress)

Mobile World Congress (MWC) is later this month in Barcelona in Spain (actually in…

• 3 min read
mwc16 , barcelona , Mobile World Congress , MWC , Tensilica , tensilican vision dsp , tensilica hifi , Breakfast Bytes

Breakfast Bytes

Autonomous Vehicles and the Semiconductor Industry: a Double-Edged Sword

A couple of weeks ago, I wrote about how automotive companies are going to need to…

• 3 min read
Automotive , sidecar , lyft , ADAS , autonomous vehicles , general motors

System, PCB, & Package Design 

How to Maximize Performance When Your Package Layout Gets Complicated

We are all familiar with it. Every year, designs get faster, smaller, and more complicated…

• 6 min read
Cadence Design Systems , SiP , Digital SiP design , IC package design , APD , package design , Allegro Package Designer

Breakfast Bytes

Datacenter in a Can

Earlier this week I wrote about the Linley Data Center Conference and how Thermal…

• 3 min read
microsoft , data center , google , thermal , cooling , power

Breakfast Bytes

"Thermal is the New Power" and Melting Butter with Your Phone

For some time now, SoC design groups have had to optimize PPA: performance, power…

• 4 min read
thermal management , PPA , thermal , power

Breakfast Bytes

Linley Data Center Conference: FPGAs and ARMs in the Cloud

Next week, February 9-10, is the Linley Data Center Conference in the Santa Clara…

• 4 min read
Altera , linley group , Linley , cloud , xilinx , ARM , datacenter , Breakfast Bytes , FPGA , cloud computing

Whiteboard Wednesdays

Whiteboard Wednesdays—Mapping Convolutional Neural Networks to the Vision P5 DSP

In this week's Whiteboard Wednesday, Chris Rowen explains how convolutional neural…

• less than a min read
Vision P5 , Whiteboard Wednesdays , IP , Chris Rowen , Computer Vision , Tensilica , convolutional neural networks , CNNs , image processing

Academic Network

Cadence Academic Network Sponsors Build 18, an Annual Freestyle Tinkering Festival…

What happens when you challenge a group of electrical and computer engineering students…

• 1 min read
build 18 , build , Cadence Academic Network , cmu , carnegie mellon univiersity

Breakfast Bytes

Modus Test Solution—Tests Great, Less Filling

Today Cadence announced the latest product in the "us" series of next-generation…

• 4 min read
modus test , low pincount test , modus , Test , codec , 2D elastic compression , test compression , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support – Empowering Learning! New Learnings from December 2015

Documentation plays a significant role in helping to understand the software. Cadence…

• 5 min read
Cadence Online Support , IC package design , Cadence Help , Cadence Application Notes , RAKs , Allegro

Academic Network

How to Start as an IT Intern and Become a Cadence Employee

Here at Cadence we are very proud to provide internships to students and graduates…

• 2 min read
Interns , Cadence Academic Network
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