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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Verification

26262 4U: Infineon and the Incisive Functional Safety Simulator

Infineon and Cadence have a bit of a history: they’ve been working together on functional…

• 2 min read
Infineon , Functional Verification , fault , ifss

Breakfast Bytes

What You See Isn't Always What You Get

I wrote earlier in the week, in my post The Alto—Forty Years On , about the origin…

• 3 min read
thanksgiving , off-topic , illusion

System, PCB, & Package Design 

A Peek into the Future of Signal Integrity with Artificial Neural Networks

Imagine how great life could be if computers or robots can do all our tedious work…

• 6 min read
PCB , EPEPS , DDR4 , deep learning , adaptive equalizers , ANN , Artificial Neural Networks , neurons , activation function , training , coefficients , machine learning , Signal Integrity , DDR , Sigrity , backchannel propagation , SystemSI

The India Circuit

Will Artificial Intelligence Take Over Art Forms?

In February last year, San Francisco’s art lovers were treated to a new kind of exhibition…

• 2 min read
DeepDream , artificial intelligence , project magenta , AI , Nsynth

Analog/Custom Design

Virtuosity: Organizing Waveform Families

When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you…

• 2 min read
ADE GXL , ADE Explorer , ADE XL , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuosity , ADE Assembler

Breakfast Bytes

The Alto—Forty Years On

I talked yesterday about the history of the Xerox PARC Alto machine, which is a computer…

• 6 min read
icarus , alto , xerox , PARC , wysiwyg

System, PCB, & Package Design 

How Can I Assess Process Variation in My IC Package Design?

In a previous blog we talked about the IC Packaging Design Variant tool. As you recall…

• 2 min read
SiP , design variants , IC package design , APD , manufacturing , 17.2

Breakfast Bytes

What's For Breakfast? Video Preview November 27th to December 1st 2017

https://youtu.be/AMMOBeri5E8 Coming from building 10 fussball table (camera Sean…

• less than a min read
silexica , JUG , ccix , chips & technologies , Jasper , cache-coherence

Breakfast Bytes

The Alto: The Machine That Changed the World

The Machine That Changed the World is actually the title of a well-known book about…

• 5 min read
icarus , computer history museum , chm , alto , xerox , PARC

Breakfast Bytes

CASPA Fuses AI and Semiconductor

CASPA is the Chinese American Semiconductor Professional Association. Once a year…

• 9 min read
deep learning , semi , caspa , Semiconductor , AI

Academic Network

Cadence Academic Network Lead Institutions

Introduction Many suggestions were spinning around the globe, many ideas are being…

• 3 min read
university , Academic Network

The India Circuit

Would You Let Your Child Ride in an Autonomous Car?

DVCon is one of the premier conferences WW for design and verification. The DVCon…

• 3 min read
DVCon India , DVcon , ADAS , autonomous vehicles

Analog/Custom Design

Dealing with AOCVs in SRAMs

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly…

• 4 min read
legato , custom/analog , Monte Carlo analysis , Monte Carlo , Spectre , Custom IC Design , Custom IC

Breakfast Bytes

Foundry Roadmaps: Intel, Samsung

I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first…

• 6 min read
Intel , ARM Techcon , Samsung , TSMC , icf , FinFET , 7nm , ARM , EUV , Techcon , FD-SOI

Verification

Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

Even today, gate-level simulation is still a major signoff step for most semiconductor…

• 2 min read
app note , Functional Verification , GLS

Breakfast Bytes

What's For Breakfast? Video Preview November 20th to 22nd 2017

https://youtu.be/aLx0C8H6qt8 Coming from Second Harvest Food Bank, San Jose (camera…

• less than a min read
thanksgiving , alto , xerox , PARC

Breakfast Bytes

IEDM Preview 2017

Every December is IEDM, the IEEE International Electron Devices Meeting (IEDM). This…

• 5 min read
Intel , IBM , 3D NAND , copper , FinFET , GlobalFoundries , MRAM , IEDM , electron devices

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplifying Fault Injection Simulations for Functional Safety…

In this week's Whiteboard Wednesday, YJ Patil answers the "What", "Why", and "How…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety

Breakfast Bytes

Jasper User Group 2017

This year's Jasper User Group (JUG) took place on 7th November. It was the 10th JUG…

• 6 min read
Jasper User Group , aruba , JUG , formal , ARM , JasperGold
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