Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 2 of…

Here we go through the application of Cadence Perspec™ System Verifier by Mediatek…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Breakfast Bytes

CDNDrive: Cadence Automotive IP Solutions

At CDNLive in Munich, Cadence's Robert Schweiger gave a walkthrough all of the things…

• 6 min read
Automotive , DSP , Vision P5 , LPDDR4 , Automotive Ethernet , Tensilica , ADAS , Breakfast Bytes

Verification

Mediatek Deploys Perspec for SoC Verification of Low Power Management

Mediatek has been using the Cadence Perspec™ System Verifier for their SoC level…

• 2 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

SoC and IP

What Will It Take to Bring DNN to Embedded?

If you missed Michelle Mao’s presentation at the recent Autosens conference in Detroit…

• less than a min read
architecture , Vision C5 , Tensilica , vision , dnn , CNN , neural nets , embedded

Breakfast Bytes

CactusNet: Moving Neural Nets from the Cloud to Embed Them in Cars

At the recent Autosens conference in Detroit, Cadence's Michelle (Xuehong) Mao presented…

• 4 min read
autosens , Vision C5 , Tensilica , cactusnet , dnn , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - A Standard Approach to Lane Margining as Defined by PCIe…

In this week's Whiteboard Wednesdays video, IP Architect Gopi Krishnamurthy explains…

• less than a min read
Whiteboard Wednesdays , PCIe Gen4 , PCIe , PCI Express

Academic Network

Academic Network at DAC 2017

Design Automatisation Conference (DAC) is the largest EDA conference in the world…

• 3 min read
dac54 , Cadence Academic Network , academia , CEDA , ACM , SIGDA , IEEE , Design Automation Conference

Breakfast Bytes

CactusNet: One Network to Rule Them All

There is a widening split in the approaches being taken by academic attempts to built…

• 5 min read
Automotive , Low Power , cactusnet , dnn , neural networks , CNN , Breakfast Bytes

Breakfast Bytes

Triple Witching Hour for Automotive

In New York, there is an occasion four times a year known as the "triple witching…

• 8 min read
electric traction , Automotive , uber , shared ownership , autonomous vehicles , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview July 10th to 14th 2017

https://youtu.be/hEhCQwICR4g Coming from the Computer History Museum, Mountain…

• less than a min read
Automotive , functional safety , deep learning , cactus net , Automotive Ethernet , Tensilica , convolutional neural nets , cactusnet , CNN

RF Engineering

Link to: 7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky…

Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp …

• less than a min read
nport , analog/RF , APS , S-parameter , Virtuoso Spectre , Spectre RF , Broadband SPICE , nport settings , RF spectre spectreRF , spectreRF , s parameter simulation

Analog/Custom Design

Virtuosity: How Can I Organize My Assistants and Toolbars?

Many things in Virtuoso can be customized, showing/hiding and configuring the layout…

• 4 min read
Analog Design Environment , ADE GXL , PAD , custom/analog , ADE Explorer , Explorer , Routing , ADE XL , ADE , VLS GXL , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ADE-XL , RF design , Virtuosity , Custom IC Design , VLS XL , Schematic , parasitics , ADE Assembler

Learning and Support

Cadence Support—Your 24x7 Self-Help Partner

Today, there is always a universal demand for learning and troubleshooting easily…

• 1 min read
Self-Help , videos , RAK , Application Notes , troubleshooting , Cadence support

Breakfast Bytes

The Kansas City Walkway Collapse—The Answer

Yesterday, I wrote about The Kansas City Hyatt Walkway Collapse . I showed a close…

• 2 min read
root cause analysis , engineering , Breakfast Bytes , kansas city walkway collapse

Breakfast Bytes

The Kansas City Hyatt Walkway Collapse—A Puzzle

It is coming up to July 4 week. Cadence will be shut down and Breakfast Bytes will…

• 3 min read
root cause analysis , engineering , Breakfast Bytes , kansas city walkway collapse

Breakfast Bytes

System in Package

At DAC, Dick James gave a fascinating presentation on system in package, or SiP,…

• 6 min read
Apple , system in package , SiP , fiji , AMD , nokia , Texas Instruments , Sony , Breakfast Bytes , CMOS image sensor

Analog/Custom Design

Virtuosity: Does Smart Software Need Help Assistants?

No, smart software like Virtuoso doesn't need Help assistants. What users of…

• 5 min read
IC 6.1 , Virtuoso Welcome Page , Cadence Online Support , Virtuoso Help Menu , Layout , Virtuoso , Cadence Help , Virtuosity , COS 2.0 , Custom IC Design , RAKs , Cadence support

Breakfast Bytes

Eating in Your Car—Mixed Signal Automotive Lunch

The Wednesday of DAC means the Cadence Mixed-Signal Lunch. For the Digital Lunch…

• 10 min read
AMS , ST , analog , Bosch , Virtuoso , digital , amkor , mixed signal , UC Berkeley , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview July 3rd to 7th 2017

https://youtu.be/iGQHYEbzcII Coming from the Porsche Museum, Stuttgart, Germany…

• less than a min read
root cause analysis , engineering , kansas city walkway collapse
CDNS - Fix Layout Hompage