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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Jul 2025 • 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

Last Chance to See Tsukiji Fish Market

This doesn’t have much to do with Cadence or semiconductors. It has a lot to do with…

Paul McLellan 4 Jul 2016 • 5 min read
tsukiji , renasas , japan , tsukiji fish market

SoC and IP

How to Create a Working IoT Sensor in One Month

Cadence and ARM have created an IoT IP reference sub-system that can speed system…

Steve Brown 28 Jun 2016 • less than a min read
sensor , IoT , ARM , IoT subsystem , IoT sensor

Whiteboard Wednesdays

Whiteboard Wednesdays—Optimizing Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen discusses optimizing neural…

References4U 28 Jun 2016 • less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , high throughput , low energy , Tensilica , neural networks

System, PCB, & Package Design 

Cadence Sigrity SystemSI Technology Highlighted at CDNLive SV 2016

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations…

TeamAllegro 27 Jun 2016 • 1 min read
PCB SI , PCB , SI , PCB Signal and power integrity , Signal Integrity , PCB design , Sigrity

Breakfast Bytes

Pieter Vorenkamp and IP at Cadence

Pieter Vorenkamp is the new(ish) senior VP and general manager of the semiconductor…

Paul McLellan 27 Jun 2016 • 2 min read
IP , Pieter Vorenkamp , Breakfast Bytes

Breakfast Bytes

An Steegen's Secrets of Semiconductor Scaling

If you were asked where in the world the most leading-edge semiconductor research…

Paul McLellan 24 Jun 2016 • 3 min read
scaling , an steegen , imec , FinFET , ITC , power , Breakfast Bytes , silicon nanowire

Breakfast Bytes

Designing for the Cloud

At the recent GSA silicon summit, there was a panel session on designing for the…

Paul McLellan 23 Jun 2016 • 4 min read
cloud , accelerator , gsa silicon summit , gsa , datacenter

Whiteboard Wednesdays

Whiteboard Wednesdays—Ubiquitous USB Interface Evolution

In this week's Whiteboard Wednesdays video, Arif Kahn details the evolution of the…

References4U 22 Jun 2016 • less than a min read
Whiteboard Wednesdays , IP , USB Type-C , USB , Arif Kahn

Breakfast Bytes

Security for IoT Is a Requirement, Not a Choice

It is hard to attend any sort of meeting to do with semiconductors without hearing…

Paul McLellan 22 Jun 2016 • 4 min read
security , IoT , Internet of Things , gsa , Breakfast Bytes

Verification

Why Do We Need a Verification Language?

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public…

teamspecman 21 Jun 2016 • 4 min read
Specman , e , Aspect Oriented Programming , yoav hollander , verification

Academic Network

What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

IEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting…

ChristinaB 21 Jun 2016 • 2 min read
ets , Cadence Academic Network

Academic Network

Students From Tianjin University in China Visit Cadence Sophia

Back in May, Professor Gilles Jacquemod and 9 engineering students from Tianjin University…

susarla 21 Jun 2016 • 1 min read
Cadence Academic Network

Breakfast Bytes

Gary Patton: What's Next? Markets and Technology

One of the keynotes at the imec technology forum last month was by Gary Patton, the…

Paul McLellan 21 Jun 2016 • 3 min read
Automotive , IoT , imec , GlobalFoundries , Breakfast Bytes

SoC and IP

Can You See Me? Putting Neural Networks in Everyday Devices

Neural networks have become very popular today due to their use in leading-edge technology…

IPGuy 20 Jun 2016 • 1 min read
CVPR , Chris Rowen , Computer Vision , Tensilica , neural networks , CNN , image processing

SoC and IP

The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets…

Steve Brown 20 Jun 2016 • 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Academic Network

CDNLive EMEA: An Intern's Perspective

CDNLive EMEA is often cited as the most exciting event of the year for Cadence. This…

ChristinaB 20 Jun 2016 • 3 min read
Cadence Academic Network , CDNLive EMEA

Breakfast Bytes

99.7% of Transistors Manufactured Are Memory

I was in Brussels a couple of weeks ago to attend imec's annual technology forum…

Paul McLellan 20 Jun 2016 • 5 min read

Breakfast Bytes

RISC-V—Instruction Sets Want to Be Free

I had never heard of the RISC-V (pronounced five, not vee) instruction set until…

Paul McLellan 19 Jun 2016 • 5 min read
risc-v , instruction set , krste asanovic , isa , RISC , UC Berkeley , instruction set architecture

Verification

IP Group @ 53rd DAC – Veni Vidi Vici

Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party…

Steve Brown 17 Jun 2016 • 2 min read
DAC , Verification IP , IP , DDR4 , LPDDR4 , SerDes
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