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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Sean and Paul DAC Walkthrough

Sean O'Kane and I wandered around the show floor during setup on Sunday and looked…

• less than a min read
54dac , chipestimatetv , Design Automation Conference

Verification

New VIP for ARM AMBA 5 CHI Issue B

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface…

• 3 min read
Verification IP , VIP , AMBA , ARM , CHI VIP

Breakfast Bytes

Guide to Austin for Newbies, and DAC Sunday Kickoff

This is my first post from DAC. I will be posting each day about the most interesting…

• 10 min read
54dac , Austin , Gary Smith EDA , iron works barbecue , franklin barbecue , #54dac , barbecue , Breakfast Bytes

Breakfast Bytes

Visual Baggage

If you have been watching my "What's for Breakfast?" weekly video previews, then…

• 7 min read
embedded vision , convolutional neural nets , autonomous vehicles , neural nets , Breakfast Bytes

Verification

See Perspec Running Accellera Portable Stimulus Examples Here and Now!

Accellera has announced the release of an Early Adopter specification of the Portable…

• less than a min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Verification

Accellera Has Done It Again! Portable Stimulus Standard Available For Review

In a press release this morning, Accellera announced availability of an Early Adopter…

• 2 min read
CDNS , Perspec , Accellera , pss , portable stimulus

Analog/Custom Design

Virtuoso Video Diary: What is Virtuoso System Design Platform?

“Any sufficiently advanced technology is indistinguishable from magic.” ― Arthur…

• 4 min read
ADE Explorer , ADE , Virtuoso Layout Suite L , Schematic Editor , Virtuoso Video Diary , Sigrity , Custom IC Design , Allegro

Academic Network

Cadence Research Workshop in Duke Kunshan University

Cadence Academic Network (CAN) hosted a Cadence Research Workshop in Duke Kunshan…

• less than a min read
Cadence Academic Network , academic workshop , academia

Breakfast Bytes

Breakfast Bytes Brought to You By... KQED?

If you live in the Bay Area, you have almost certainly heard KQED's Forum program…

• 6 min read
kqed , wired , mixed reality , fake reality , pbs , virtual reality , fake news , augmented reality

Analog/Custom Design

Virtuosity: New Modgen and Row-Based Placement Rapid Adoption Kits

Cadence Rapid Adoption Kits (RAKs) are designed to help users quickly adopt new technologies…

• 3 min read
Row Region , EAD , Row Template , Modgen On Canvas , MODGEN , Rapid Adoption Kit , Virtuoso Placer , RAK , VLS GXL , Layout , Virtuosity , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Row-Based Placement

Breakfast Bytes

Samsung Foundry Forum: Beyond FinFET and FD-SOI

This is the third post on the second Samsung Foundry Day held recently. The first…

• 4 min read
IBM , envm , emram , horizontal nanosheet , rf-soi , GlobalFoundries , EUV , Breakfast Bytes , FD-SOI

Whiteboard Wednesdays

Whiteboard Wednesdays - 3 Market Forces Driving Commercial IP Adoption

In this week's Whiteboard Wednesdays video, Tom Hackett explains the 3 forces driving…

• less than a min read
Design IP , Whiteboard Wednesdays , IP , interfaces

Breakfast Bytes

What's For Breakfast? Video Preview June 19th to June 23rd 2017

https://youtu.be/QtKiDx9yXAY Coming from the Staten Island Ferry NY (camera…

• less than a min read
DAC , 54dac , Design Automation Conference

Breakfast Bytes

Samsung Foundry Forum: EUV

This is the second post on the second Samsung Foundry Day held recently. The first…

• 5 min read
Samsung , samsung foundry , EUV , Breakfast Bytes

Analog/Custom Design

Virtuosity: I've Learned to Customize RTT Simulations...Bingo!

The Real-Time Tuning (RTT) assistant is one of the most powerful features of ADE…

• 4 min read
Analog Design Environment , custom/analog , ADE Explorer , Explorer , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuosity , Custom IC Design

Breakfast Bytes

Samsung Foundry Forum: Roadmaps

I attended the second Samsung Foundry Forum. As seems to be traditional for foundries…

• 4 min read
8nm , Samsung , samsung foundry , Qualcomm , 5nm , 7nm , 10nm , EUV , Breakfast Bytes

Verification

A Brief Introduction to Xcelium

Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the…

• less than a min read
Low Power , digital mixed signal , Functional Verification , Multi-Core , xcelium , parallel simulation

Breakfast Bytes

Pre-Silicon Software Development with Protium and Palladium Platforms

We've already had CDNLive EMEA, but here is a look at a presentation from CDNLive…

• 5 min read
debug , android , Protium , Palladium , embedded software , software development , linux , Breakfast Bytes

Breakfast Bytes

Schematic-Driven Simulation and Layout of Complex Photonic ICs

Photonics is transmitting data through fiber optic cables. As such, photonics is…

• 5 min read
PhoeniX Software , Lumerical , silicon photonics , Virtuoso , photonics , Breakfast Bytes
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