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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Intelligent System Design for Automobiles of the Future

There's a lot going on in the automotive market. The three big things are electric…

• 4 min read
Automotive , ADAS

System, PCB, & Package Design 

BoardSurfers: Avoid Iterations with Your Manufacturing Partner – Detect and Address…

Some things are rare, good or bad, but they do happen from time to time. And, some…

• 2 min read
DesignTrue , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays – What is Happening at the USB IF Standards Meetings?

In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the next-generation…

• less than a min read
Whiteboard Wednesdays , USB

System, PCB, & Package Design 

IC Packagers: Bend in Both Directions with J-Loop Bond Wires

Let’s talk about wire bonding for a quick minute. Still a favorite for many of you…

• 4 min read
IC Packaging , APD , SiP Layout

Breakfast Bytes

GLOBALFOUNDRIES After the Pivot

At SEMICON West I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to get an update…

• 4 min read
globalfound , semicon , 22fdx , 12fdx , FD-SOI

定制IC芯片设计

Virtuoso 视频日记: Reliability Setup 的新功能

今天的博客重点介绍了可 reliability options 表单和整体 reliability setup 的增强功能。这个博客是我们迷你博客系列的一部分。我们会在每周二…

• 1 min read
Chinese blog , ADE Explorer , Virtuoso Video Diary , ADE Blog Series , reliability analysis , Custom IC Design , ADE Assembler

Life at Cadence

Cadence and the Expanding Presence of Women in Tech Conferences

Cadence sponsors several different tech conferences throughout the year. We use these…

• 4 min read
Insights on Culture , Culture , STEM , IEEE WIE ILC , women , VerveCon , diversity

SoC and IP

Is the Role of Test Chips Changing at Advanced Foundry Nodes?

Test chips are becoming more widespread and more complex at advanced process nodes…

• 3 min read
Design IP , IP , cadence , PCIe Gen4 , IP integration , ip cores , Ethernet , semiconductor IP , PCI Express

Breakfast Bytes

Will American Scooters Follow Chinese Bikes?

I spent the July 4 weekend in San Diego. My public service announcement is that if…

• 5 min read
Automotive , scooter , app , smarphone , bike

Analog/Custom Design

Virtuoso Meets Maxwell: Learn Your Moves – We’re Doing an Edit-in-Concert

This blog showcases the Edit-in-Concert technology available in the Cadence Virtuoso…

• 4 min read
Edit-in-Concert , Virtuoso Meets Maxwell , Advanced Node , Virtuoso RF , Virtuoso , Custom IC Design

Verification

How to Verify Performance of Complex Interconnect-Based Designs?

With more and more SoCs employing sophisticated interconnect IP to link multiple…

• 2 min read
Verification IP , Interconnect Workbench , Interconnect Validator , SoC , Performance modeling , AMBA , ATP , ARM , System Verification

Breakfast Bytes

Sunday Brunch Video for 14th July 2019

https://youtu.be/HO3cViPU6Mw Made at Slovensky Raj, Slovakia (camera Gary Bengier…

• less than a min read
sunday brunch

Breakfast Bytes

The Mercedes Benz Museum and the Invention of the Automobile

Recently, I was in Stuggart, Germany. This is the home to the headquarters of both…

• 5 min read
Automotive , mercedes benz

PCB、IC封装：设计与仿真分析

Cadence LPDDR4设计IP通过TSMC 16FFC FinFET 车规工艺验证

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ Cadence Memory IP for LPDDR4…

• less than a min read
PCB , SI , Chinese blog , 仿真分析 , LPDDR4 , 中文 , Sigrity , 信号完整性

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes – Using Generate Trunks

The Trunk Generation feature is the founding piece that offers incremental productivity…

• 2 min read
Trunk generation , Interactive Routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , Layout EXL , Layout Suite , trunk creation , Virtuoso , Generate Trunk , EM Trunk Optimization , Custom IC Design , space based router , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

NXP: Can Silicon Valley Really Crack the Automakers' Code?

The second panel at the recent NXPConnect was about Silicon Valley versus traditional…

• 7 min read
Automotive , NXP , ADAS

Computational Fluid Dynamics

VPLP Design: Revolutionizing Hydrofoil Design with Advanced CFD Simulation Techn…

Hydrofoils have unleashed the speed of sailing boats since the last two America’s…

• 4 min read

定制IC芯片设计

Virtuosity: 过滤波形

在接下来的几周内，Virtuosity和Virtuoso Video Diary博客将重点关注 Virtuoso®ADE Assembler , Virtuoso…

• less than a min read
Chinese blog , ADE Explorer , plotting , plot , Filtering , ViVA , Virtuosity , ADE Blog Series , Custom IC Design , ADE Assembler

Breakfast Bytes

Carry: Electronics

The last two days I have written about carry in mechanical calculating devices. See…

• 7 min read
carry , adder
CDNS - Fix Layout Hompage