Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Denali’s never-ending list of parties expands to Flash Memory Summit: August 18

Seems like the list of Denali parties for Summer 2010 never ends. Denali is heavily…

• less than a min read

SoC and IP

Verification tips and GLOBALFOUNDRIES low-power process to be discussed in Denali…

Going to DAC? Interested in making your verification processes more effective? Interested…

• less than a min read

SoC and IP

Last call for Denali’s DAC party: Anaheim, June 14

It’s the Denali DAC party for 2010. The big one. With the bells and whistles. With…

• less than a min read

Verification

Bloggers and Journalists and Gadflies, Oh My!

There has been quite a bit of discussion out in the blogosphere about the similarities…

• 3 min read
DAC , Functional Verification , EDA , Blogging , blogs

SoC and IP

An inconvenient truth about using DDR3 SDRAM for embedded designs

DDR (double data rate) memory chips mounted on DIMMs have long been the mainstay…

• 3 min read

Verification

EDA360 And The "Paperback Computer"

Have you ever heard an assertion that's so intriguing and farsighted that it sticks…

• 7 min read
events , DAC , IP , paperback computer , innovation , metric driven verification (MDV) , Functional Verification , Advanced Node , EDA360 , Verification IP modeling , EDAC

SoC and IP

Storage Analyst Jim Handy says “NAND Cache is Back!”

Storage analyst and Grand Poobah Jim Handy has just released a free White Paper titled…

• 2 min read

SoC and IP

Kingston shows HyperX USB 3.0 SSD prototype at Computex

Earlier, this blog reported on OCZ’s Enyo USB 3.0 SSD and now at a private event…

• 1 min read

Verification

Making an EDA360 System Realization Investment Through Standards Support

Cadence is a sponsor of the Open SystemC Initiative (OSCI) standards organization…

• less than a min read
TLM , C-to-Silcon , OSCI , ESL

SoC and IP

Introduced at Computex: OCZ’s speedy RevoDrive brings PCIe SSD to consumer-class…

PC add-on vendor OCZ plays in several high-performance PC component markets including…

• 1 min read

Verification

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL…

• 1 min read
CTOS , TLM , C-to-Silicon , Synthesis , HLS

SoC and IP

Hitachi’s Z HDDs: Will 2.5mm less height make a difference? For SSDs?

Hitachi just shaved 2.5mm off of the top of its 2.5-inch laptop hard drives, producing…

• 1 min read

SoC and IP

More details on and system-design implications of the Hitachi-LG Data Storage HyDrive…

As discussed last week in this blog, Hitachi-LG Data Storage (HLDS)--an OEM vendor…

• 3 min read

System, PCB, & Package Design 

What's Good About AMS Simulator And Cursors? You’ll Need The SPB16.3 Release To See

With the SPB16.3 release of AMS Simulator , several new cursor enhancements are available…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Schematic

SoC and IP

ST Microelectronics’ SPEAr1300 embedded MCU features 600MHz dual-core ARM Cortex…

A few days ago, this blog discussed the “big resistor” model of SDRAM power consumption…

• 2 min read

Verification

TLM 2.0 As Part Of The EDA360 Vision

Ann Steffora Mutschler recently covered in her blog the progress the industry has…

• 1 min read
TLM , virtual platform , TLM 2.0 , EDA360 , virtual prototype , SystemC , Synthesis , System Design and Verification

System, PCB, & Package Design 

Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence…

Is there anyone who does not carry a mobile communication device anymore? Sending…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , Allegro 16.3 , APD , webinar , SI analysis and modeling

SoC and IP

How does a hybrid SSD/optical drive make sense?

Some combinations like chocolate with peanut butter, ice cream with peanuts and chocolate…

• 1 min read

Verification

EDA360 Is More Than Design IP Plus Software Drivers

I checked my Linked-In messages the other day and saw a survey by Girish Patil with…

• 2 min read
IP , Functional Verification , Virtual Chips , Phoenix , inSilicon , VIP , EDA360 , Sand
CDNS - Fix Layout Hompage