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Featured

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
Corporate 20 Sep 2025 • 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
Corporate 17 Sep 2025 • 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
Reela Samuel 2 Sep 2025 • 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
cdns - all_blogs_categories

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Blog - Post List

Latest blogs

定制IC芯片设计

Virtuoso: 新序曲- Cadence Virtuoso “第18.1 交响乐” 的前奏曲

Cadence Virtuoso is soon presenting a new symphony..."Symphony No. 18.1". Stay tuned…

Rishu Misri Jaggi 13 Sep 2018 • less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 3

I gave an introduction to speculative execution and the vulnerabilities that have…

Paul McLellan 13 Sep 2018 • 7 min read
meltdown , architecture , processor , Spectre , speculative execution

Breakfast Bytes

What's For Breakfast? Video Preview September 17th to 21st 2018

https://youtu.be/3drxzhMFGD8 Coming from PCB West (camera Sean) Monday: HOT CHIPS…

Paul McLellan 12 Sep 2018 • less than a min read
Intel , CDNLive India , cascade lake , NVIDIA , Samsung , hot chips , ARM

Verification

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

Join us on September 14th for a free one-hour webinar on the finer aspects of the…

XTeam 12 Sep 2018 • less than a min read
uvm , Functional Verification , webinar , Duolos , uvm register layer

Analog/Custom Design

Virtuoso: The Next Overture - Congestion Analysis with a New Perspective

Watch out for the exclusive set of routing features, along with the newly introduced…

Parula 12 Sep 2018 • 3 min read
Congestion Analysis , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Space-based Router , Routing , Virtuoso Advanced Release , Congestion Assistant , New in EDA , Custom IC Design , Virtuoso New Design , Design Planner , Custom IC

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 2

I gave an introduction to speculative execution and the vulnerabilities that have…

Paul McLellan 12 Sep 2018 • 4 min read
meltdown , processor , Spectre , cache , speculative execution , foreshadow

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 1

At HOT CHIPS, one of the "keynotes" was actually a panel of what I'll call industry…

Paul McLellan 11 Sep 2018 • 8 min read
Intel , meltdown , processor , Spectre , cache , ARM , speculative execution , foreshadow

Breakfast Bytes

CDNLive India

CDNLive India took place last week. As usual, I made the long trip from California…

Paul McLellan 10 Sep 2018 • 5 min read

System, PCB, & Package Design 

New Sigrity 3D Workbench Used in Designing and Optimizing Next Generation High-Speed…

2018 is going to be remembered as the year of 3D for Sigrity. As part of Cadence…

Sigrity 8 Sep 2018 • 2 min read
Sigrity 2018 release , 3D Workbench , Mechanical Structures , CDNLive , High Speed Structure Optimization , PowerSI 3D EM Extraction Option , 3DEM , 3D , Sigrity , High Speed design

PCB、IC封装:设计与仿真分析

升级到Allegro17.2-2016的10大理由之4:行业领先的背钻能力

背钻的发展历程 15年来,在很多电子设计中处理5Gbps或更高频率的高速接口布线已越来越常见。在信号过孔上存在Stub的情况下,高速信号换层将会对信号完整性产生巨大影响…

TeamAllegro 8 Sep 2018 • less than a min read
PCB , Chinese blog , Allegro 17.2 , 背钻 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro升级17.2 , Allegro

PCB、IC封装:设计与仿真分析

升级到Allegro17.2-2016的10大理由之3:新的PAD编辑器——不只是一个新GUI

客户反馈是产品改善的关键 当您在理解Allegro 17.2-2016发行版的特点和优势时,我可以猜到您在想什么。“哦不,他们对我的工作环境做了什么破坏?”如果您已使用Allegro多年了…

TeamAllegro 8 Sep 2018 • less than a min read
Chinese blog , Allegro 17.2 , 钻孔 , 掩模 , 禁止区 , PCB设计 , 中文 , 焊盘 , Allegro升级17.2 , Allegro

RF Engineering

Measurement of Phase Noise in Oscillators

The other day, I happened to sneak out some time for myself after having sent the…

Jommy 7 Sep 2018 • 1 min read
HBnoise , HB , Spectre RF , pnoise , phase noise , harmonic balance , pss , Oscillator

Analog/Custom Design

Virtuoso: The Next Overture – Introducing Design Planner

Watch out for our new layout design capability that allows you to plan more efficiently…

Rishu Misri Jaggi 7 Sep 2018 • 2 min read
Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC , Layout Editing

Breakfast Bytes

PCAST: The President's Council of Advisors on Science and Technology

In January 2017, a report Ensuring Long-Term U.S.Leadership in Semiconductors was…

Paul McLellan 7 Sep 2018 • 6 min read
electronics resurgence initiative , Hennessy , magestic , pcast , eri , darpa

Breakfast Bytes

What's For Breakfast? Video Preview September 10th to 14th 2018

https://youtu.be/iv9wdAVB6vg Coming from CDNLive India (camera Seena Shankar) Monday…

Paul McLellan 6 Sep 2018 • less than a min read
meltdown , CDNLive India , CDNLive , Spectre , hot chips

Breakfast Bytes

Numbers Everyone Should Know

At the recent HOT CHIPS, Paul Turner of Google Project Zero talked about numbers…

Paul McLellan 6 Sep 2018 • 5 min read
cpu speed , cache , networking

Breakfast Bytes

GLOBALFOUNDRIES Drops 7nm to Focus on Other Geometries

GF put out a press release last week with the title GF Reshapes Technology Portfolio…

Paul McLellan 5 Sep 2018 • 4 min read
Intel , AMD , Samsung , TSMC , 5nm , GlobalFoundries , 7nm , EUV

Academic Network

APAC IC Design Contests

China Graduate IC Design Contest Contest Duration: April – August 2018 This is Cadence…

Tracy Zhu 5 Sep 2018 • 1 min read
apac , Cadence Academic Network

Whiteboard Wednesdays

Whiteboard Wednesdays - What You need to Know About ISO26262-2018 2nd Edition

In this week's Whiteboard Wednesdays video, the first in a multi-part series, Scott…

References4U 4 Sep 2018 • less than a min read
Whiteboard Wednesdays , ISO 26262
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CDNS - Fix Layout Hompage

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