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Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
Cadence Japan 8 Jan 2026 • less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
Corporate 6 Jan 2026 • 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
Cadence Japan 22 Dec 2025 • less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
KomalJohar 17 Dec 2025 • 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Academic Network

Academic Network at VLSI-DAT Symposium in Taiwan 2018

2018 was the second year Cadence Academic Network supported the VLSI-DAT Symposium…

Tracy Zhu 25 May 2018 • 1 min read
VLSI , university , Taiwan , Cadence Academic Network , academia

Breakfast Bytes

GDPR Starts Today

You are probably subscribed to a number of email newsletters. No doubt you have been…

Paul McLellan 25 May 2018 • 6 min read
Facebook , gdpr

Breakfast Bytes

Embedded Vision: Seeing 20,000X Improvement

This week it is the Embedded Vision Summit in Santa Clara. Over the last few years…

Paul McLellan 24 May 2018 • 6 min read
Embedded Vision Summit , Tensilica , neural network

Breakfast Bytes

What's For Breakfast? Video Preview May 28th to June 1st 2018

https://youtu.be/UEAZjA-_xrE Coming from Embedded Vision Summit (camera Sean)…

Paul McLellan 23 May 2018 • less than a min read
DAC , pegasus , HOT , Heart of Technology , imec , 55DAC

Breakfast Bytes

MEMS Design Competition: The Envelope Please...

The Cadence Academic Network sponsored a MEMS design contest over the last couple…

Paul McLellan 23 May 2018 • 3 min read
Cadence Academic Network , CDNLive , MEMS

Whiteboard Wednesdays

Whiteboard Wednesdays - The Truth about Designing for Automotive Functional Safe…

In this week’s Whiteboard Wednesday, Tom Hackett challenges conventional wisdom and…

References4U 22 May 2018 • less than a min read
Automotive , Whiteboard Wednesdays , functional safety , automotive IP , ISO 26262 , ADAS

Breakfast Bytes

Accelerating AI: ...Present and Future

Yesterday I wrote about the first part of Krste Asanović's presentation Accelerating…

Paul McLellan 22 May 2018 • 5 min read
artificial intelligence , risc-v , Krste Asanović , sifive

Breakfast Bytes

Accelerating AI: Past...

SiFive does a quarterly series of tech talks, not necessarily directly to do with…

Paul McLellan 21 May 2018 • 9 min read
artificial intelligence , risc-v , neural networks , Krste Asanović , sifive

Breakfast Bytes

CGTN China 24 Interview

https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week…

Paul McLellan 18 May 2018 • less than a min read
China , china24 , cgtn

Analog/Custom Design

Virtuosity: What's New in Run Plan – Part II

The Run Plan assistant in Virtuoso ADE Assembler has proved to be one of the most…

Yagya Mishra 18 May 2018 • 2 min read
Run Plans , custom/analog , Analog Simulation , ADE , Virtuoso Analog Design Environment , calibration , Virtuoso , Analog Design Environment , Virtuosity , Run Plan , runplan , Custom IC Design , Custom IC , Assembler

Breakfast Bytes

Achronix Grew 700% Last Year...eFPGA is a Thing

I don't normally write about the FPGA market. There are three reasons for this. First…

Paul McLellan 18 May 2018 • 6 min read
Intel , embedded fpga , achronix , intel custom foundry , FPGA

Breakfast Bytes

CDNDrive: ISO 26262...Chapter 11

At CDNLive EMEA Robert Schweiger laid out his perspective on the automotive market…

Paul McLellan 17 May 2018 • 5 min read
Automotive , functional safety , CDNLive , CDNLive EMEA , Tensilica , ISO 26262

Whiteboard Wednesdays

Whiteboard Wednesdays - An Introduction to Compute In-Memory

In this week’s Whiteboard Wednesday, Marc Greenberg introduces the concept of “Compute…

References4U 16 May 2018 • less than a min read
Whiteboard Wednesdays , Memory , processor , DDR , Compute In-Memory

Breakfast Bytes

TSMC: Mobile, HPC, IoT, Automotive...and Packaging

This is the third post about the TSMC Technology Symposium that was held on May 1st…

Paul McLellan 16 May 2018 • 11 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , mobile

Breakfast Bytes

What's For Breakfast? Video Preview May 21st to 25th 2018

https://youtu.be/AmlYRYzIHtY Coming from my office (camera Sean, guest star Alexa…

Paul McLellan 15 May 2018 • less than a min read
accelerating AI , CDNLive , embedded vision , Tensilica , gdpr , MEMS

The India Circuit

Inspiration, Networking and Food For Thought

Recently I had the opportunity to attend the Society of Women Engineers (SWE) Conference…

Chandrika Durbha 15 May 2018 • 4 min read
society of women engineers , SWE , women leaders

Breakfast Bytes

CDNLive: Testing Times in Munich

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning…

Paul McLellan 15 May 2018 • 9 min read
modus test , CDNLive , Scan test , modus , imec , Test

Academic Network

Status of Verification Education in Academia

Since I’ve started working for Cadence Academic Network three years ago, when talking…

Anton Klotz 14 May 2018 • 3 min read
survey , Cadence Academic Network , Functional Verification , young professionals , Incisive simulator

Breakfast Bytes

Agile Development of Custom Hardware

It was back in 2016 that I first heard about RISC-V, and the Raven implementation…

Paul McLellan 14 May 2018 • 5 min read
bag , chisel , agile software development , waterfall , raven , agile hardware development , UC Berkeley , Agile
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