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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Computational Fluid Dynamics

CFD Wind Studies for Ship Superstructures

Besides resistance, seakeeping and propulsion, wind loads play an important role…

• 2 min read
CFD , naval archicture , Marine Engineering , shipping , marine , fine/marine , Wind Study , Computational Fluid Dynamics , fluid dynamics , IMO regulations , CFD Applications , simulation software , NUMECA , naval

Breakfast Bytes

The Framework Laptop and Right to Repair

You might have heard some discussion about "the right to repair" or R2R. Some of…

• 5 min read
framework laptop , right to repair , r2r

Verification

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

• 2 min read
Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface

Analog/Custom Design

Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow…

• 4 min read
Analog Digital Designs , Mixed-Signal Designs , Trim Shapes , Virtuoso , Virtuoso Innovus Interoperability , Virtuosity , Innovus , ICADVM20.1 , leConvertTrimmedShapesToPRStyle , leReportTrimmedShapesInCustomStyle , Custom IC Design , Interoperable IC Designs , Virtuoso Layout Suite

Life at Cadence

AI Unleashes Chip Designer Productivity

EDA has a history of enabling breakthrough designer productivity. AI in EDA isn’t…

• 5 min read
cerebrus , ai-driven , digital , implementation

Breakfast Bytes

Cadence: Sustainable by Design

Last week, Cadence published the Cadence Sustainability Report 2021 (link at the…

• 5 min read
sustainability report 2021 , sustainability , power

Computational Fluid Dynamics

This Week in CFD #468

It's a sunny 81 degrees here in Fort Worth as I type this and after going outside…

• less than a min read
CFD , Computational Fluid Dynamics , fluid dynamics , Mesh Generation

Verification

Who Inspires You? - An SVG Women's History Month Spotlight

This month, we join millions celebrating and recognizing the achievements of women…

• 6 min read

Breakfast Bytes

March 2022 Update: Intel Video, India, Apple

Amazingly, it is already the last Friday in March (and so the last Friday in Q1,…

• 4 min read
Intel , Apple , transistor , m1 ultra , update , India

Learning and Support

What is IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution

Are you searching for a scalable standard architecture for enabling test reuse and…

• 2 min read
digital badge , blended training , training bytes , Cadence certified , online training , Cadence Support Portal , Cadence support

Digital Design

Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Sup…

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries…

• 6 min read
debug , Routing , Unconstrained Path , congestion , OCV , SOCV , RAKs

Breakfast Bytes

DVCon: UVM Birds of a Feather

At the recent DVCon 2022, there was a UVM Birds of a Feather meeting. UVM stands…

• 5 min read

System, PCB, & Package Design 

BoardSurfers: Specifying Layer Information for Multi-Layer Rigid and Flex Stacku…

To manufacture a product that performs as you intended, it is imperative that you…

• 5 min read
APD+ , 17.4 , Signal Intregrity , BoardSurfers , layer stacks , Layout , 17.4-2019 , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

System Analysis Knowledge Bytes: The Road Ahead for Sigrity - An Interview with Brad…

In this blog, Brad Griffin (Product Management Group Director for Sigrity Marketing…

• 7 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , Sigrity X , Voltus IC Power Integrity Solution , Sigrity PowerSI , Power Integrity , Sigrity OptimizePI , Signal Integrity , Sigrity XtractIM , Sigrity PowerDC , Sigrity SPEEDEM , SystemSI , Clarity 3D Solver , T2B , Allegro PCB Designer

Breakfast Bytes

3D Packaging Versus 3D Integration

A couple of weeks ago it was time for the 18th International Conference and Exhibition…

• 4 min read
system-in-package , SiP , chiplets , 3DIC

Computational Fluid Dynamics

Toyota Drastically Reduces Simulation Time with Automatic CFD Pre-Processing

Creating a detailed CFD model for automotive applications normally requires a huge…

• 2 min read
CFD , Automotive , automotive engineering , toyota , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software , Omnis

Breakfast Bytes

DesignCon is Back In-Person and Cadence Will Be there

DesignCon is coming up April 5th to 7th. It takes place in the Santa Clara Convention…

• 3 min read
DesignCon , system analysis , Signal Integrity , photonics , thermal

RF /マイクロ波設計

μWaveRiders:AWRソフトウェアを使用したRFカスケード性能の分析と最適化

RF設計者にとっての重要な課題は、ノイズと歪みの性能のためにRF系を最適化することです。 RF系のノイズと歪みを決定することは、カスケード分析として知られています…

• less than a min read
Cascade analysis , AWR Design Environment , RF Budget measurements , awr , RF cascade analysis , RF cascade , RF design , Circuit Design , microwave office , japanese blog , RF Cascade Performance , RF cascade analysis software , RF chain , Visual System Simulator(VSS)

RF Engineering

μWaveRiders: Using AWR Software to Analyze and Optimize RF Cascade Performance

A significant challenge for RF designers is the optimization of an RF chain for noise…

• 3 min read
Cascade analysis , featured , AWR Design Environment , RF Budget measurements , awr , RF cascade analysis , RF cascade , RF design , Circuit Design , microwave office , Visual System Simulator (VSS) , RF Cascade Performance , RF cascade analysis software , RF chain
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