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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

The 2022 Kaufman Dinner

On May 12th, it was the Kaufman Award Ceremony and Banquet at which Cadence's CEO…

• 5 min read
kaufman dinner , Kaufman Award , Anirudh Devgan , kaufman award 2021

Breakfast Bytes

Sunday Brunch Video for 15th May 2022

https://youtu.be/F-dN8wy-iNc Made at Steve Brown's "moving to San Diego party" …

• less than a min read
sunday brunch

Academic Network

Searching on Cadence Support Is Now Even Easier!

The Cadence Learning and Support Portal is useful to academia in many ways: Online…

• 1 min read
Cadence Academic Network , Cadence Online Support , online training , university program

Breakfast Bytes

New Book: Hyperscale Computing Trends 2022

Cadence has a new book out. Written by Frank Schirrmeister and myself, it is called…

• 3 min read
hyperscaler , Schirrmeister , McLellan , book

Verification

Demystifying CXL.cache

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past…

• 3 min read
CXL , Functional Verification , pcie 5 , VIP , PCIExpress , coherency , verification

System, PCB, & Package Design 

IC Packagers: Three Reasons for Allegro Package Designer Plus Users to Move to OrCAD…

The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is…

• 1 min read
IC Packaging , APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , 17.4 QIR4

Breakfast Bytes

What Is High-NA EUV?

I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes…

• 5 min read
asml , imec , SPIE , high-na euv , EUV

Computational Fluid Dynamics

CadenceLIVE Silicon Valley 2022 - CFD Track: Seven Reasons to Attend

On June 8th and 9th, it is CadenceLIVE Americas. It is planned to be in-person at…

• 3 min read
Computational Fluid Dynamics , fluid dynamics , CFD events , CFD Applications , simulation software

Breakfast Bytes

Open RAN Phase 2

I first wrote about Open RAN in my post Fourth 4G Network Goes Live in Japan . Open…

• 4 min read
oran , mobile , o-ran alliance , openran

Verification

Renesas Leverages Palladium + System VIP Solution for System Verification and Performance…

Verifying bus performance by analyzing bandwidth and latency over time in chips is…

• 5 min read

Digital Design

Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With…

Low-Power synthesis is one of the important stages in the full IC flow. Here, you…

• less than a min read
Low Power , Genus , Digital Implementation , Synthesis , power optimization

PCB、IC封装：设计与仿真分析

Clarity 3D Solver 2022版本闪亮登场

最新的电磁设计同步分析功能有助于提高 IC、IC 封装和高性能 PCB 设计的速度 美国加州圣何塞(DesignCon)—楷登电子（Cadence Design…

• less than a min read
网格划分 , Chinese blog , ml , 机器学习 , EM分析 , PCB设计 , 电磁分析 , 设计同步分析 , EM , Clarity 3D Solver , 人工智能 , 刚柔结合 , AI , clarity

Breakfast Bytes

TechInsights: Foundation for the Future

The second day of the Linley Spring Processor Conference opened with a keynote by…

• 3 min read
linley processor conference , Linley , reverse engineering , techinsights

PCB設計／ICパッケージ設計

ASCENT: デザインのコンストレイントを簡単な方法で設定する

コンストレイント(制約条件)は、PCB デザインの要件が論理的、物理的の両方の観点で満たされることを保証するためのルールです。コンストレイントは、パーツ、ピン、ネットなどの様々なオブジェクトに定義できます…

• less than a min read
System Capture , 17.4 , 17.4-2019 , Allegro System Capture , japanese blog , ASCENT , Allegro

PCB、IC封装：设计与仿真分析

汽车行业合规与功能安全指南：ISO 26262 标准出台十周年

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Happy 10th Birthday ISO…

• less than a min read
Chinese blog , 中文 , 功能安全 , 汽车 , ISO 26262

Digital Design

Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis…

A Logic Synthesis is a process of optimizing the design's area, timing, and power…

• less than a min read
Genus , Flows , Logic Design , Optimize , Synthesis

Breakfast Bytes

Linley: Western Digital's RISC-V Strategy

Western Digital acquired SanDisk in 2016. In 2017, Martin Fink, then the CTO of Western…

• 3 min read

PCB設計／ICパッケージ設計

BoardSurfers: IPC-2581の利用によるレイヤースタックアップデータの受け渡し

設計意図やスタックアップ情報を設計の初期段階のうちに製造部門や製造委託先と共有しておけば、製品設計に影響を与え製品納入を遅らせてしまうような製造やアセンブリ関連の問題を回避することができます…

• less than a min read
PCB manufacturing , BoardSurfers , IPC-2581 Consortium , 17.4-2019 , japanese blog , Allegro PCB Editor , IPC-2581 , Allegro

Breakfast Bytes

Sunday Brunch Video for 8th May 2022

https://youtu.be/xADMKcqKLNg Made on Communication Hill with Sheep (camera Carey…

• less than a min read
sunday brunch
CDNS - Fix Layout Hompage