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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—Ubiquitous USB Interface Evolution

In this week's Whiteboard Wednesdays video, Arif Kahn details the evolution of the…

• less than a min read
Whiteboard Wednesdays , IP , USB Type-C , USB , Arif Kahn

Breakfast Bytes

Security for IoT Is a Requirement, Not a Choice

It is hard to attend any sort of meeting to do with semiconductors without hearing…

• 4 min read
security , IoT , Internet of Things , gsa , Breakfast Bytes

Verification

Why Do We Need a Verification Language?

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public…

• 4 min read
Specman , e , Aspect Oriented Programming , yoav hollander , verification

Academic Network

What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

IEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting…

• 2 min read
ets , Cadence Academic Network

Academic Network

Students From Tianjin University in China Visit Cadence Sophia

Back in May, Professor Gilles Jacquemod and 9 engineering students from Tianjin University…

• 1 min read
Cadence Academic Network

Breakfast Bytes

Gary Patton: What's Next? Markets and Technology

One of the keynotes at the imec technology forum last month was by Gary Patton, the…

• 3 min read
Automotive , IoT , imec , GlobalFoundries , Breakfast Bytes

SoC and IP

Can You See Me? Putting Neural Networks in Everyday Devices

Neural networks have become very popular today due to their use in leading-edge technology…

• 1 min read
CVPR , Chris Rowen , Computer Vision , Tensilica , neural networks , CNN , image processing

SoC and IP

The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Academic Network

CDNLive EMEA: An Intern's Perspective

CDNLive EMEA is often cited as the most exciting event of the year for Cadence. This…

• 3 min read
Cadence Academic Network , CDNLive EMEA

Breakfast Bytes

99.7% of Transistors Manufactured Are Memory

I was in Brussels a couple of weeks ago to attend imec's annual technology forum…

• 5 min read

Breakfast Bytes

RISC-V—Instruction Sets Want to Be Free

I had never heard of the RISC-V (pronounced five, not vee) instruction set until…

• 5 min read
risc-v , instruction set , krste asanovic , isa , RISC , UC Berkeley , instruction set architecture

Verification

IP Group @ 53rd DAC – Veni Vidi Vici

Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party…

• 2 min read
DAC , Verification IP , IP , DDR4 , LPDDR4 , SerDes

Analog/Custom Design

Waveform Thumbnails

Wouldn't it be great if you could see your plots directly on the schematic? Well…

• 2 min read
Explorer , waveforms , waveform thumbnails

Academic Network

Open Source Raspberry Pi Design Files for Allegro and OrCAD Tools

The Raspberry Pi has firmly established itself as a household name by providing a…

• 2 min read
university , Cadence Academic Network , university program

Breakfast Bytes

Seamless Verification

At DAC, Cadence had their now traditional verification lunch. Brian Fuller returned…

• 6 min read
DAC 2016 , DAC , palladium z1 , virtual platform , Palladium , dac53 , Emulation , FPGA prototyping , simulation , Breakfast Bytes , Formal verification , verification

Academic Network

Cadence Technology Days at MIET

On 21 April, Cadence and the Moscow Institute for Electronics Technologies (MIET…

• 1 min read
MIET , Cadence Academic Network , academic workshop , academia , Russia

Academic Network

Visiting KAUST

Cadence Academic Network is a worldwide activity; therefore, the team members are…

• 2 min read
university , Cadence Academic Network , academic workshop , KAUST

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Fiber Weave Effect—Zig-Zag Routing? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces the interactive conversion of…

• 3 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Academic Network

Academic Track at CDNLive EMEA

From May 2 to May 4, Cadence once again hosted their hugely popular user conference…

• 2 min read
Cadence Academic Network , CDNLive , MEMS Design Contest , CDNLive EMEA
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