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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Training Insights: Migrating from Allegro DE-HDL to Allegro X System Capture

Explore the strategic and technical benefits of transitioning to Allegro X System…

• 2 min read
PCB , webinar , Design Entry HDL , PCB design , allegro x , Allegro , Allegro X System Capture

Learning and Support

GenAI-Powered ASK AI Assistant Now Live on Cadence ASK Portal

You might remember the blog about the GenAI Feature on Cadence ASK that we published…

• 1 min read

中文技术专区

瑞芯微 RK2118 集成 Cadence Tensilica HiFi 4 DSP 提供强大的音频处理

搭载 Cadence Tensilica HiFi 4 DSP的 Rockchip RK2118 系统级芯片（SoC）已于 2024 年第四季度投入量产。这款尖端的…

• less than a min read
DSP , 音频处理 , HiFi , SoC , Tensilica

System, PCB, & Package Design 

PCB Design Workflow Using Sigrity X for Signal and Power Integrity Analysis

Jasmine Vital Muniz, Electrical Engineer, OLogic, Inc. While many electronic design…

• 1 min read
PCB , SIPI , Sigrity X , Power Integrity , SI/PI Analysis , Signal Integrity

SoC and IP

Redefining SoC Design: The Shift to Secure Chiplet-Based Architectures

The semiconductor industry is undergoing a paradigm shift from monolithic system…

• 5 min read
security , Automotive , chiplets , physical ai , SoC

中文技术专区

Enkl Sound 利用 Tensilica HiFi DSP 优化音频技术，缔造无与伦比的卓越音质

在快速发展的音频技术领域，Enkl Sound Copenhagen 宛如一座创新的灯塔，将经典斯堪的纳维亚设计与前沿数字声音处理技术相融合，而促成这种融合的核心…

• less than a min read

Corporate News

Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications

Next-generation consumer and automotive audio is becoming increasingly sophisticated…

• 4 min read
news story , featured , Symmetric Multiprocessing , audio , Silicon Solutions , HiFi , Front Page Press Release , SMP , Tensilica , SSG , Xtensa

Verification

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium , Palladium , xcelium , VDE , helium , System Verification

中文技术专区

Cadence UCIe IP 在 Samsung Foundry 的 5nm 汽车工艺上实现流片成功

我们很高兴能在此宣布，Cadence 基于UCIe 标准封装 IP 已在 Samsung Foundry 的 5nm 汽车工艺上实现首次流片成功。这一里程碑彰显了我们持续提供高性能车规级IP解决方案…

• less than a min read

RF Engineering

Empowering RF Power: Must-See Video Series for AWR Users!

Calling all AWR Microwave and RF designers—getting the most out of your tools just…

• 1 min read
RF , RF Simulation , analog/RF , Cadence Academic Network , AWR Design Environment , Virtuoso RF , Electromagnetic analysis , Analyst 3D FEM EM Simulator , RF design , AWR Microwave Office , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS)

System, PCB, & Package Design 

Cadence Customers Share Experiences with Revolutionary PCB Design Methodology

PCB design teams are often caught in a repetitive cycle of design and simulation…

• 3 min read
Automotive , si/pi , Sigrity X Aurora , MIPI , PCB design , ADAS , allegro x

Academic Network

Accelerating Innovation: The SolarCar at Virginia Tech Team

At a time when sustainability and innovation are beautifully coming together, the…

• 2 min read
featured , Cadence Academic Network , CFD Simulations , Solar Car

SoC and IP

Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos

As we move through 2025, the momentum generated by Cadence continues to energize…

• 2 min read
PCIe 7.0 , PCIe , PCI-SIG

Learning and Support

Analog and Digital IC Design Flows: The Past, Present, and Future of Electronics

Curious to see how your IC design skills (Analog/Digital) stack up—or where to level…

• 8 min read
college grads , digital design , blended training , AIML , specifications , xcellium , Custom IC flow , onboarding , Genus , Analog IC Flow , schematic design , GDSII , chip design , Tempus , pegasus , ASIC flow , RTL , video , Self Learning , tutorial , 3DIC , Cadence Online Support , APR , Digital IC Flow , Virtuoso ADE , place and route , Cadence training , digital badges , learninggap , training bytes , Virtuoso , Design and Verification , Semiconductor , Spectre , learnfast , Post Layout , Digital Implementation , GenAI , Innovus , physical design , Layout design , mobile , Virtuoso Layout , learning and support , Pre Layout , Verisium Manager , Quantus , online training , simulation , silicon , Digital Physical Design , Tape-out

Digital Design

Elevate Your EDA Skills: Achieve Unmatched PPA with Genus Synthesis Solution

As the electronic design automation (EDA) landscape continues to evolve, the importance…

• 4 min read
training , training bytes , Optimize , Genus Synthesis Solution , Synthesis , online training

System, PCB, & Package Design 

Discover Cadence Community Forums Resources for Tcl Scripting

In the world of PCB design and IC packaging, automation is key to enhancing productivity…

• 2 min read
PCB , Allegro X AI , cadence , awr , Tcl Scripting , Cadence Community Forums , community forum , SPB , PCB design

Corporate News

Driving the Future of High-Speed Computing with PCIe 7.0 Innovation

Escalating compute processing demands from generative and agentic AI applications…

• 4 min read
controller IP , Verification IP , featured , agentic ai , PHY , PCIe 7.0 , PCIe , HPC , high-performance computing , PCI-SIG

Digital Design

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus , Digital Implementation , AI

Cadence Japan

ケイデンスのエージェント型AIがSoC/システム・エンジニアリングの時間を数ヶ月短縮

最新のSoC設計の複雑さに対応するにあたり、AIを活用したチップ設計は必要不可欠となっています。設計に活用するエージェント型AIの段階、ケイデンスの関連製品などについては…

• less than a min read
news story , SoC , japanese blog , AI
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