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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Breakfast Bytes

Will the Semiconductor Industry Reach $1T by 2030?

I'm going to summarize the case for "yes" from McKinsey & Co, and the case for "it…

• 5 min read
DesignCon , semiconductor industry , growth rate

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre回路シミュレータでのDSPFポストレイアウトネットリストの使用

DSPFは、様々なネットリストフォーマットの１つで、Spectre®を含むEDAツールで、トランジスタレベルでのレイアウト後の抽出されたデザインを表現するために使用されます…

• 1 min read
spectre aps , post-layout simulation , EMIR Analysis , EMIR Simulation , DSPF , netlist , Spectre , japanese blog , Spectre X Simulator , EMIR

Computational Fluid Dynamics

ASME Turbo Expo 2022 Focuses on a Carbon-Neutral Future by 2050

This year's ASME Turbo Expo Conference aims to accelerate the transition of the energy…

• 1 min read
CFD , turbomachinery , Computational Fluid Dynamics , fluid dynamics , Turbo , simulation

Academic Network

BarCamp at DATE 2022

It is still a time of online conferences, unidirectional presentations, hardly any…

• 2 min read
DATE , conference , Cadence Academic Network , BarCamp , virtual reality

System, PCB, & Package Design 

Training Insights: Bridging the Gap Between Design and Analysis with Sigrity Aur…

Join Cadence Training and Principal Application Engineer Vladimir Papic for this…

• 3 min read
IDA , Sigrity Aurora , Power Integrity , Signal Integrity , Topology Explorer , Training Insights , Sigrity , Allegro PCB Editor

Computational Fluid Dynamics

The Era of Fluid Simulations in Hollywood

VFX effects for fluid flow in movies are created using fluid simulation platforms…

• 4 min read
CFD , fluid simulations , simulation platforms , VFX , fluid animation , movies , Disney , fluid dynamics , Hollywood , Navier Stokes

Breakfast Bytes

DesignCon 2022: The 224G Show

At DesignCon, there is often a theme that comes through, and this year there were…

• 4 min read
224G , pam4 , extended long reach , pam6 , 112g , long reach , SerDes

Analog/Custom Design

Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Si…

Read this blog for an introduction to the Custom IC Design methodology and the key…

• 5 min read
Virtuoso Schematic Editor , Analog Design Environment , custom/analog , ADE Explorer , Explorer , Analog Simulation , analog , Virtuoso Visualization and Analysis XL , ADE , Virtuoso Analog Design Environment , Spectre , Schematic Editor , ViVA , Virtuosity , ICADVM20.1 , AMS simulation , mixed signal , analog design , usability , Custom IC Design , Custom IC , IC6.1.8 , Assembler , Schematic , custom design technology , ADE Assembler

Computational Fluid Dynamics

Meet Our Marine CFD Experts at the Euromaritime Exhibition

On June 28-30 2022, the Maritime Community meets again in Marseille at this biennial…

• 1 min read
CFD , naval archicture , Marine Engineering , marine , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , naval

Breakfast Bytes

Secure Before You Fabricate

One thing that I have come into contact with recently is the notion that the US defense…

• 5 min read
security , Mil-Aero , prototyping , Protium , Palladium , Emulation

Verification

Device Training for High Speed DRAMs

As the device frequencies and the data rates go up with every new generation of Interface…

• 3 min read
Verification IP , ddr5 , VIP , JEDEC , Training Modes , lpddr5 , lpddr5x , memory models , DDR5DIMM

Breakfast Bytes

The Convergence of Photonic and Electronic ICs

At the recent DesignCon in Santa Clara, one of the keynotes was by John Bowers of…

• 4 min read
DesignCon , silicon photonics , photonics

Spotlight Taiwan

Cadence Perspec驗證在異質多核心行動處理器之應用

作者:Vic Chen, Principal Application Engineer, Cadence可攜式測試與刺激標準(Portable Test and…

• 1 min read
PSS Methodology , Perspec , cadencelive taiwan , perspec system verifier , taiwanese blog

Breakfast Bytes

Sunday Brunch Video for 10th April 2022

https://youtu.be/fmV1XVY-ZiI Made at Coyote Hills Regional Park (camera Carey) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro PCB Ed…

The HotFix SPB17.40.028 of 17.4-2019 of Allegro® PCB Editor has been rolled out and…

• 3 min read
17.4 , BoardSurfers , padstack , DesignTrue DFM , QIR4 , 17.4-2019 , Constraints , Allegro PCB Editor , Allegro

Breakfast Bytes

Ericsson Cellular Network at TÜV Rheinland Test Center

At the end of March, I went to the TÜV Rheinland Test Center. TÜV stands for Technischer…

• 4 min read
Automotive , Ericsson , tüv , mobile

Breakfast Bytes

Identity Is the New Perimeter

On March 10th, Black Hat organized a webinar called Identity is the New Perimeter…

• 9 min read
security , black hat , orange

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 13: Analog Fault S…

While the analog and mixed-signal components are the leading source of test escapes…

• 4 min read
Automotive , legato , ICADVM20 , functional safety , analog fault simulation , analog , training bytes , Virtuoso , Analog IC Design videos , Spectre , 1 , Virtuoso Video Diary , aging , Custom IC Design , IC6.1.8 , reliability , Legato Reliability , ADE Assembler

PCB設計／ICパッケージ設計

2022年3月リリース、Cadence OrCAD / Allegro17.4-2019 HotFix SPB17.40.028の新機能ハイライト

OrCAD® および Allegro®のHotFix 028 (QIR 4, アプリケーションのスプラッシュ画面で は “2022” と表示されます) の更新プログラムが…

• less than a min read
17.4 , PCB Editor , 17.4-2019 , OrCAD , Allegro System Capture , japanese blog , Allegro PCB Editor , Pulse , Allegro
CDNS - Fix Layout Hompage