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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

DesignCon 2019: Is this the Year?

2019 has started --- is this the year of advanced packaging, where system design…

• 1 min read
DesignCon , packaging

Verification

Verification of ML IP and Specman—Our Hackathon Project

If you are lucky enough and your company spends a few working days each year on a…

• 7 min read
ml , Specman , Specman/e , Specman e , machine learning , specman elite , verification coverage , verification

Breakfast Bytes

AMD Keynote at CES

As I said in my post about CES last week (see my post Consumer Electronics: 5G, AI…

• 9 min read
Lisa Su , CES , AMD

Breakfast Bytes

Tensilica at CES

Tensilica has been attending CES for many years, before it was acquired by Cadence…

• 3 min read
hifi 5 , CES , Vision P6 , Tensilica , dna100

Analog/Custom Design

Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using…

In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting…

• 3 min read
Extraction , Quantus

Breakfast Bytes

Gordon Moore Killed the Oakland Tribune

The Oakland Tribune closed down in 2016. It remains to be seen if the San Jose Mercury…

• 7 min read
newspapers , journalism

Breakfast Bytes

Consumer Electronics: 5G, AI, and Air Taxis

I'm sure you've heard the great marketing catchphrase that "What happens in Vegas…

• 5 min read
Apple , Consumer Electronics , CES , ces2019

Analog/Custom Design

Virtuosity: Saving Time, Effort, and Money with Express Pcells

Use the Express Pcell feature and see for yourself how you can save time, effort…

• 3 min read
Advanced Node , Express Pcell , pcell , Virtuoso , Virtuosity , Layout design , Custom IC Design , Virtuoso Layout Suite , Parameterized Cell , Custom IC , Layout Editing

Breakfast Bytes

SiFive: The Magnificent Seven

At least for now, I think that the most significant of the RISC-V processor companies…

• 7 min read
risc-v , ARM , sifive

Breakfast Bytes

Breakfast Nibbles: Predictions for 2019

It is the start of the year, so time to provide my predictions for 2019. These are…

• 5 min read
5G , Automotive , China , Memory , deep learning , 3nm , cloud , DRAM , 5nm , neural networks , EUV

Breakfast Bytes

2018: A Year of Breakfasts

It's the start of a new year. Tomorrow, I'll pick out what I think that the big trends…

• 5 min read
security , Automotive , artificial intelligence , China , deep learning , photonics , 5nm , EUV

Breakfast Bytes

Sunday Brunch Video for 8th January 2019

https://youtu.be/tAMYvJJcPy0 Made at Vieira Park, San Jose (camera Carey Guo) Wednesday…

• less than a min read
interconnect , risc-v , esperanto , ruthenium , maxion , swerv , IEDM

Breakfast Bytes

RISC-V Cores: SweRV and ET-Maxion

December was the first RISC-V summit at the Santa Clara Convention Center. I covered…

• 6 min read
Western Digital , risc-v , esperanto , maxion , swerv

Digital Design

Glitch Noise Analysis and Fixing with Tempus

Every design engineer knows something about glitch but for many the details are a…

• 5 min read
SI , Tempus , STA , delay , noise , glitch , Signal Integrity , crosstalk , signoff , silicon signoff , Sign off , timing

Breakfast Bytes

IEDM: The World After Copper

I remember Gary Patton, the CTO of GLOBALFOUNDRIES, telling me once that research…

• 9 min read
interconnect , cobalt , copper , 3nm , contact , imec , amat , 5nm , IEDM , rubidium

Breakfast Bytes

150th Anniversary of the Periodic Table of the Elements

Happy New Year, and welcome to another year of Breakfast Bytes. This year is the…

• 5 min read
mendeleev , periodic table

Breakfast Bytes

Sunday Brunch Video for 1st January 2019

https://youtu.be/my0o9-PD-a8 Made at the Cadence EBC (camera Sean) Monday: CES Preview…

• less than a min read
The Economist , CES , flying , puzzle , hotels

Verification

Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification…

Recently, Renesas Electronics Corporation faced a challenge. They were developing…

• 1 min read
Specman , Functional Verification , Renesas , e , success

Breakfast Bytes

Silent Night

Happy Christmas from Breakfast Bytes. It's Christmas Eve 2018, and 200 years ago…

• 2 min read
silent night , anniversary , off topic , Christmas
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