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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
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Blog - Post List

Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview June 19th to June 23rd 2017

https://youtu.be/QtKiDx9yXAY Coming from the Staten Island Ferry NY (camera…

• less than a min read
DAC , 54dac , Design Automation Conference

Breakfast Bytes

Samsung Foundry Forum: EUV

This is the second post on the second Samsung Foundry Day held recently. The first…

• 5 min read
Samsung , samsung foundry , EUV , Breakfast Bytes

Analog/Custom Design

Virtuosity: I've Learned to Customize RTT Simulations...Bingo!

The Real-Time Tuning (RTT) assistant is one of the most powerful features of ADE…

• 4 min read
Analog Design Environment , custom/analog , ADE Explorer , Explorer , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuosity , Custom IC Design

Breakfast Bytes

Samsung Foundry Forum: Roadmaps

I attended the second Samsung Foundry Forum. As seems to be traditional for foundries…

• 4 min read
8nm , Samsung , samsung foundry , Qualcomm , 5nm , 7nm , 10nm , EUV , Breakfast Bytes

Verification

A Brief Introduction to Xcelium

Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the…

• less than a min read
Low Power , digital mixed signal , Functional Verification , Multi-Core , xcelium , parallel simulation

Breakfast Bytes

Pre-Silicon Software Development with Protium and Palladium Platforms

We've already had CDNLive EMEA, but here is a look at a presentation from CDNLive…

• 5 min read
debug , android , Protium , Palladium , embedded software , software development , linux , Breakfast Bytes

Breakfast Bytes

Schematic-Driven Simulation and Layout of Complex Photonic ICs

Photonics is transmitting data through fiber optic cables. As such, photonics is…

• 5 min read
PhoeniX Software , Lumerical , silicon photonics , Virtuoso , photonics , Breakfast Bytes

Breakfast Bytes

Cadence at DAC

Yes, it's nearly here, the 54th Design Automation Conference in Austin, Texas (and…

• 7 min read
DAC , Joe Costello , expert bar , Cadence Theater , 54dac , Denali Party , Accellera , cooley troublemaker panel , #54dac , pss , cadence lunches , Breakfast Bytes , portable stimulus standard

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the…

• less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

What's For Breakfast? Video Preview June 12th to June 16th 2017

https://youtu.be/oikFfm15nw8 Coming from Samsung@First (camera Sean) Monday…

• less than a min read
kqed forum , embedded vision , Samsung , computer history museum , samsung foundry forum , EUV , FD-SOI

Digital Design

2017 Annual HLS Survey Results

As many of you know, Cadence (more correctly, “I”) recently performed an industry…

• 4 min read
High-Level Synthesis , survey , Stratus , HLS

Breakfast Bytes

Rowen: How to Start an Embedded Vision Company

The last presentation that I'll cover in its own post from this year's Embedded Vision…

• 6 min read
Chris Rowen , Embedded Vision Summit , embedded vision , Tensilica , Breakfast Bytes

Breakfast Bytes

Bier Goggles: 1000X in 3 Years

Jeff Bier heads up the Embedded Vision Alliance (and, in his day job, he heads up…

• 4 min read
Embedded Vision Summit , deep neural networks , Embedded Vision Alliance , BDTI , dnn , neural networks , Breakfast Bytes

Breakfast Bytes

Deep Understanding, Not Just Deep Vision

The keynote on the second day of the Embedded Vision Summit was by Jitendra Malik…

• 10 min read
convolutional neural nets , dnn , neural networks , CNN , neural nets , Breakfast Bytes

Breakfast Bytes

Lifting the Veil on Hololens

The opening keynote at the Embedded Vision Summit in Santa Clara was by Marc Pollefeys…

• 7 min read
hololens , microsoft , Embedded Vision Summit , Tensilica , vision , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview June 5th to June 9th 2017

https://youtu.be/C7nOhT8ey7g Coming from Cadence Cafeteria (camera Sean) …

• less than a min read
DAC , 54dac , palldium , Protium , embedded vision , Embedded Vision Alliance , silicon photonics , #54dac , Design Automation Conference

Breakfast Bytes

Embedded Vision Summit: "It's a Visual World"

"It's a visual world," Tim Ramsdale of ARM said at one point in the recent Embedded…

• 12 min read
embedded vision , deep neural networks , Tensilica , convolutional neural networks , neural nets , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Vision C5 DSP: A Solution to Current Challenges and Trends…

In this week's Whiteboard Wednesdays video, Megha Daga talks about how Cadence did…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Virtuoso System Design Platform

Cadence was already talking about chip-package-board back in 2000 when I was putting…

• 3 min read
package , board , 2.5D packagin , Virtuoso , 3D packaging , interposer , Sigrity , Custom IC , Breakfast Bytes , Allegro
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