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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

DAC Wednesday: Verification Lunch, Books, and Bagpipes

For my coverage of the first two days of DAC, see my posts DAC Monday: Gaming, IoT…

• 10 min read
DAC , 56dac , Design Automation Conference

Breakfast Bytes

DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali

It was the second day of DAC yesterday. If you were here, you probably saw some of…

• 6 min read
DAC , 56dac , Design Automation Conference

Whiteboard Wednesdays

Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM…

In this week’s Whiteboard Wednesdays video, Amol Borkar continues his discussion…

• less than a min read
Whiteboard Wednesdays , Vision Q7 DSP , SLAM

System, PCB, & Package Design 

IC Packagers: The (Copper) Pillars of Modern Design

Wire bonding has been around forever. Flip-chip mounting? That’s been around for…

• 7 min read
IC Packaging , IC Packaging and SiP , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to…

• 4 min read
APD , PCB Editor , PCB design , SiP Layout

Breakfast Bytes

DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley…

The Design Automation Conference is in Las Vegas this year. If you are here and want…

• 11 min read
DAC , 56dac , Design Automation Conference

Academic Network

How to Show You’re a Verification Engineer?

There is always a need for verification engineers in the microelectronics industry…

• 1 min read
Specman , Cadence Academic Network , verification

System, PCB, & Package Design 

IC Packagers: Dealing with Large Forms in Low Resolution Screens

Our packages and boards are becoming complex and so are the design tasks we perform…

• less than a min read
IC Packaging and SiP , Allegro Package Designer

Digital Design

Need Help with Liberate Commands and Parameters?

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you…

• 1 min read
parameter , Liberate AMS , liberate blog , liberate trio , Liberate LV , Commands , Liberate Variety , Liberate MX , Cadence Help , Digital Implementation , Liberate , Liberty

Breakfast Bytes

Spectre X: Same Accuracy, New Speed

This morning at DAC, Cadence announced the Spectre X Simulator, the latest version…

• 2 min read
Circuit simulation , Spectre , cadence cloud , spectre x

Breakfast Bytes

Sunday Brunch Video for 2nd June 2019

https://youtu.be/T2VZUEW1ucc Made at Protium Hardware Lab (camera Sean) Monday:…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

SI工程师如何分析多千兆位串行链路、内存及接口

作者：Ken Willis 早在2007年，Cadence推动了对IBIS标准的扩展，即算法模型接口（AMI），可以模拟多千兆位串行链路接口。这与通道（与传统电路相对…

• less than a min read
SI , Chinese blog , ddr5 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , 信号完整性 , SI分析与建模

Life at Cadence

Appreciating Our Employees

Recognizing the Outstanding Effort that Makes Cadence Successful Cadence hires the…

• 1 min read
awards

Breakfast Bytes

ESD Alliance CEO Outlook: The Leading Edge, Chiplets, Design Costs, Security, and…

The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel…

• 10 min read
ceo outlook , esd alliance

Verification

Got IP Security Questions? This Luncheon at DAC Has Answers

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you…

• 2 min read
security , DAC , luncheon , DAC 2019 , Accellera

Breakfast Bytes

Embedded Vision: Seeing Round Corners, and Reasoning on Microcontrollers

May is a month that seems to have many things associated with it. "Sell in May and…

• 10 min read
deep learning , Embedded Vision Summit , google , mit media lab , neural network

Verification

DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety…

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week…

• 5 min read
security , 5G , DAC , DAC2019 , prototyping , palladium z1 , Safety , tortuga logic , Protium , Emulation , ARM , AI

Analog/Custom Design

Spectre Tech Tips: Spectre APS Save Overview - Part 1

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use…

• 6 min read
save statement , spectre aps , nestlvl , pwr=subckt , save=selected , save=lvlpub , save=allpub , currents=all , subcktprobelvl , Spectre , currents=selected , pwr=devices , Spectre Waveform Writing , pwr=total , pwr=all , save option

Breakfast Bytes

Verific, 20 Years Terrific

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well…

• 4 min read
verific , Stratus , JasperGold
CDNS - Fix Layout Hompage