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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

The India Circuit

Never Lose Your Way Again With These Nifty Maps

CDNLive India took place a few weeks ago and we are just trying to catch our breath…

• 4 min read
artificial intelligence , CDNLive India , Netradyne , CDNLive , Edge Computing , HD mapping , machine learning , AI

Analog/Custom Design

Virtuoso - The Next Overture: Introducing Simulation Driven Routing

The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis…

• 2 min read
Interactive Routing , EAD , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , electrically aware design , Simulation-driven interactive routing , Mixed-Signal , Layout , Virtuoso , Custom IC Design , Custom IC

Breakfast Bytes

CDNLive India: Invecas and FD-SOI

Today it is GTC, the GlobalFoundries Technology Conference. I will be there and I…

• 5 min read
foundation IP , 22fdx , Innovus , Invecas , GlobalFoundries , FD-SOI

Breakfast Bytes

EDPS: Design Process in Milpitas

For the second year, the Electronic Design Process Symposium (EDPS) took place in…

• 8 min read
eda education , deep learning , EDPS

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之5：如何进行“叠层设计”？

在这我们谈论的不是您的叠层设计跟其他人比怎么样，而是您设计的PCB层叠结构，是刚性板、柔性板、刚柔板，或者使用了镶嵌技术。层叠的定义，更具体而准确的层叠的定义，是至关重要的…

• less than a min read
PCB , Chinese blog , 布线 , PCB设计 , 中文 , MCAD-ECAD , Allegro PCB Editor , Allegro PCB编辑器 , 刚柔结合设计 , Allegro升级17.2 , 刚柔结合 , Allegro

Breakfast Bytes

Jaswinder's Only Job Interview

On Labor day, I didn't get the day off since I was in Delhi. I had to labor, not…

• 6 min read
bengaluru , Cadence India , Noida

Breakfast Bytes

What's For Breakfast? Video Preview September 24th to 28th 2018

https://youtu.be/NYsYkQzZADo Coming from SAP Center, San Jose (camera Sean) Monday…

• less than a min read
National Instruments , GTC , Kaufman Award , EDPS , RF design , Invecas , GlobalFoundries , esd alliance

Breakfast Bytes

Samsung Galaxy S9's Application Processor

At this year's HOT CHIPS, Jeff Rupley of Samsung presented the application processor…

• 5 min read
Samsung , m3 , 10nm , galaxy

Breakfast Bytes

The New Tensilica DNA 100 Deep Neural-network Accelerator

Today, at the beautiful Tegernsee resort outside Munich in Germany, Cadence announced…

• 6 min read
xnnc , android neural networks , dna 100 , caffe , TensorFlow , Tensilica , neural network

Whiteboard Wednesdays

Whiteboard Wednesdays - Standalone AI Processor: Tensilica DNA 100 Processor IP for…

In this week's Whiteboard Wednesdays episode, Megha Daga describes the new Tensilica…

• less than a min read
Whiteboard Wednesdays , dna 100 , AI

PCB、IC封装：设计与仿真分析

为什么电源完整性(PI)是个“热”话题——如何进行电/热协同仿真

在设计新一代产品时，我们共同追求的目标都是“更快，更小，更便宜”。然而当这与更长的电池寿命和更低的功耗要求相遇时，就向我们提出了艰巨的设计挑战。唯一可以肯定的是…

• less than a min read
PCB , 热 , PI , Chinese blog , 电源完整性 , 电热协同仿真 , Power Integrity , PCB设计 , 中文 , Sigrity , PowerDC

Breakfast Bytes

HOT CHIPS: Some HOT Deep Learning Processors

If there was a theme running through the recent HOT CHIPS conference in Cupertino…

• 5 min read
Intel , deep learning , processor , NVIDIA , machine learning , hot chips , ARM

Breakfast Bytes

CDNLive India: Asynchronous Design

Every few years the idea of doing completely clockless design gets proposed again…

• 5 min read
CDNLive India , jasper gold , Texas Instruments , Formal verification

PCB、IC封装：设计与仿真分析

三维建模与电磁场分析新工具——3D Workbench

在Cadence公司刚刚发布的Sigrity 2018版本中，介绍了全新的三维建模与电磁场仿真工具——3D Workbench。它具有当前市场上主流3D CAD…

• 1 min read
Chinese blog , 电源完整性 , 3D Workbench , 3D EM , PCB设计 , 中文 , PowerSI 3D EM , 3D CAD , Sigrity , 信号完整性 , Sigrity最新版

Breakfast Bytes

Intel's Cascade Lake: Deep Learning, Spectre/Meltdown, Storage Class Memory

At the recent HOT CHIPS in Cupertino, Sujal Vora of Intel gave a look inside the…

• 4 min read
Intel , meltdown , cascade lake , deep learning , storage class memory , optane , Spectre , 3dxpoint

定制IC芯片设计

Virtuoso: 新序曲- Cadence Virtuoso “第18.1 交响乐” 的前奏曲

Cadence Virtuoso is soon presenting a new symphony..."Symphony No. 18.1". Stay tuned…

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC

Breakfast Bytes

Spectre/Meltdown & What It Means for Future Design 3

I gave an introduction to speculative execution and the vulnerabilities that have…

• 7 min read
meltdown , architecture , processor , Spectre , speculative execution

Breakfast Bytes

What's For Breakfast? Video Preview September 17th to 21st 2018

https://youtu.be/3drxzhMFGD8 Coming from PCB West (camera Sean) Monday: HOT CHIPS…

• less than a min read
Intel , CDNLive India , cascade lake , NVIDIA , Samsung , hot chips , ARM

Verification

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

Join us on September 14th for a free one-hour webinar on the finer aspects of the…

• less than a min read
uvm , Functional Verification , webinar , Duolos , uvm register layer
CDNS - Fix Layout Hompage