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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

Breakfast Nibbles: Predictions for 2019

It is the start of the year, so time to provide my predictions for 2019. These are…

• 5 min read
5G , Automotive , China , Memory , deep learning , 3nm , cloud , DRAM , 5nm , neural networks , EUV

Breakfast Bytes

2018: A Year of Breakfasts

It's the start of a new year. Tomorrow, I'll pick out what I think that the big trends…

• 5 min read
security , Automotive , artificial intelligence , China , deep learning , photonics , 5nm , EUV

Breakfast Bytes

Sunday Brunch Video for 8th January 2019

https://youtu.be/tAMYvJJcPy0 Made at Vieira Park, San Jose (camera Carey Guo) Wednesday…

• less than a min read
interconnect , risc-v , esperanto , ruthenium , maxion , swerv , IEDM

Breakfast Bytes

RISC-V Cores: SweRV and ET-Maxion

December was the first RISC-V summit at the Santa Clara Convention Center. I covered…

• 6 min read
Western Digital , risc-v , esperanto , maxion , swerv

Digital Design

Glitch Noise Analysis and Fixing with Tempus

Every design engineer knows something about glitch but for many the details are a…

• 5 min read
SI , Tempus , STA , delay , noise , glitch , Signal Integrity , crosstalk , signoff , silicon signoff , Sign off , timing

Breakfast Bytes

IEDM: The World After Copper

I remember Gary Patton, the CTO of GLOBALFOUNDRIES, telling me once that research…

• 9 min read
interconnect , cobalt , copper , 3nm , contact , imec , amat , 5nm , IEDM , rubidium

Breakfast Bytes

150th Anniversary of the Periodic Table of the Elements

Happy New Year, and welcome to another year of Breakfast Bytes. This year is the…

• 5 min read
mendeleev , periodic table

Breakfast Bytes

Sunday Brunch Video for 1st January 2019

https://youtu.be/my0o9-PD-a8 Made at the Cadence EBC (camera Sean) Monday: CES Preview…

• less than a min read
The Economist , CES , flying , puzzle , hotels

Verification

Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification…

Recently, Renesas Electronics Corporation faced a challenge. They were developing…

• 1 min read
Specman , Functional Verification , Renesas , e , success

Breakfast Bytes

Silent Night

Happy Christmas from Breakfast Bytes. It's Christmas Eve 2018, and 200 years ago…

• 2 min read
silent night , anniversary , off topic , Christmas

Digital Design

Patterns, a Unified Language between Design and Manufacturing

There will be no design without manufacturing and manufacturing is mainly about patterns…

• 3 min read
pattern analysis , machine learning , yield , design for manufacturing , DFM

PCB、IC封装：设计与仿真分析

DDR5的时代已经到来

本文翻译自Cadence “Breakfast Bytes” 专栏作者Paul McLellan文章" DDR5 Is on Our Doorstep "。 space…

• less than a min read
Chinese blog , ddr5 , DDR4 , Micron , TSMC , DRAM , 中文

The India Circuit

7 Trends We Saw In 2018

I did at 2017 retrospective last year and looking back at 2018 there was a lot that…

• 3 min read
2019 , 2018 in review

Breakfast Bytes

Off Topic: Are You Smarter Than Google?

It's the day before Cadence is shut down for the holidays. Breakfast Bytes will resume…

• 7 min read
off topic , monty hall problem , are you smarter than google

Analog/Custom Design

Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download…

• 2 min read
Virtuoso ICADV12.3 , Analog Design Environment , ICADV12.3 , Routing , IC 6.1 , Mixed-Signal , Virtuoso , Schematic Editor , IC6.1.7 , Virtuoso IC6.1.7 , Virtuoso Layout Suite , ADE Assembler

Analog/Custom Design

Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing…

• 7 min read
spectre aps , Spectre EMIR , Virtuoso ADE , Spectre , EMIR , Voltus-Fi XL

Verification

Verification Reflections on 2018

In my predictions for 2018 I had identified five key trends driving verification…

• 5 min read
security , functional safety , verification

Breakfast Bytes

Top 10 Hotel Pet Peeves

When it comes to hotels, I have simple tastes. As long as the bed is comfortable…

• 10 min read
hotel , travel

System, PCB, & Package Design 

10 Things You Might Have Missed in 2018

We’re sure it’s been a busy year for you. So busy that you might have missed the…

• 2 min read
PCB , Cadence Design Systems , Symphony , Power Integrity , PCB design , Sigrity , DFM , Allegro
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