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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

• 2 min read
Embedded Systems Conference , RTL , System Design and Verification , ESL

Verification

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

• 1 min read
System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

Verification

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

• 1 min read
High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect

Analog/Custom Design

Connectivity and Constraint Driven Design: Will It Ever Become The Standard for Custom…

In the late 70's and early 80's system level PCB and Digital IC physical design evolved…

• 6 min read
VSR , Virtuoso IC 6.1.3 , Virtuoso Custom Placer , CAD , IC 6.1.4 , Custom IC Design , custom design technology , VCP

System, PCB, & Package Design 

What's Good About Schematic Drawing Standards?

This past week, there has been a very interesting discussion on the "icu-pcb-forum…

• 2 min read
PTF , PCB design , Schematic , Allegro

Verification

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

• less than a min read
DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Verification

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

• 1 min read
IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Welcome to Richard Goering

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering…

• less than a min read
Industry Insights , Functional Verification , EDA

Analog/Custom Design

What’s all the Hoopla with PDKs?

At a purely technical level, Process Design Kits are fairly innocuous. They are used…

• 2 min read
IC 6.1 , Virtuoso , PDK , Custom IC Design , Process Design Kit

Analog/Custom Design

Analog Design Validation: What is Your Recipe for Success?

Every analog circuit design goes through some kind of electrical validation step…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

SoC and IP

DRAMs: Historically, how bad is this downturn?

DRAMs: Another look at how bad it is: Last week, we (finally) published our summary…

• 3 min read

Verification

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

• 2 min read
validation , embedded world conference , System Design and Verification , ISX , ARM , verification

Analog/Custom Design

Virtuoso, the SATs, and The Dark Knight - Part I

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight…

• 1 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS"…

• 5 min read
SaaS , Functional Verification , Harry The ASIC Guy , DVcon , Xuropa

Analog/Custom Design

Automated Digital Block Implementation Using Virtuoso

Have you ever found yourself laying out a digital block in Virtuoso where you have…

• 2 min read
VSR , Virtuoso Custom Placer , Virtuoso , Custom IC Design , VCP

Digital Design

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important…

Having consistency and correlation in timing analysis across the design flow is …

• less than a min read
EDN , encounter , Digital Implementation , Encounter Timing System

Verification

Is Software Engineering Engineering? You Decide!

Last night when I was waiting for my daughter to finish orchestra rehearsal (she…

• 3 min read
System Design and Verification , failure tolerance , software engineering , design metrics

Analog/Custom Design

Calculating Large Signal Phase Noise Using Transient Noise Analysis

My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group. We…

• 2 min read
PLL , MMSIM , RF design , Circuit Design , Simulators , Custom IC Design

Digital Design

Get on Board With Bus Guides

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you…

• 2 min read
Bus Guides , encounter , 8.1 , Digital Implementation
CDNS - Fix Layout Hompage