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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Video Demo: Spice 2.0 - The ABCs of APS

Designers have had ubiquitous access to powerful SMP/multicore systems for years…

• less than a min read
APS , SMP , Spice 2.0 , multicore , Custom IC Design

System, PCB, & Package Design 

What's Good About FPGA Capabilities in Capture? Download the SPB16.2 Release and…

With the SPB16.2 release, a few new FPGA enhancements have been added. In recent…

• 1 min read
SPB 16.2 , PCB design , UCF , xilinx , Allegro , FPGA: PCB

Verification

How to Save OS Boot Time In Your SystemC Virtual Platform With Save and Restore

One advantage of using a virtual platform or virtual prototype over real hardware…

• 2 min read
open virtual platforms , virtual platform , System Design and Verification , QEMU virtual platform , Incisive , SystemC analysis , System simulation and analysis , George Frazier , SystemC , Hardware/software co-verification , QEMU

Verification

OVM Is The Safest Bet By 2:1

One of the questions verification engineers will be asking as they head to DVCon…

• 1 min read
SystemVerilog , OVM , VIP , e , DVcon , eRM

Verification

The Real Story on HLS With ANSI-C/C++ vs. SystemC

There's a new post worth reading for anyone interested i n the current state of…

• 3 min read

Verification

SystemC TLM2 based Virtual Prototype Demo at DVCon

DVCon 2009 promises much news about System level design and verification. With Open…

• less than a min read
co-verification engineer , virtualization , Co-verification link , virtual platform , System Design and Verification , embedded software , Incisive , virual platform , system validation/verification engineer , virtual protoype , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , Incisive Software Extensions , ISX , Hardware/software co-verification , Jason Andrews , ESL , architect , QEMU

Verification

C-to-Silicon Does Not Require a Library Characterization

One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis…

• less than a min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , ESC , C-to-Silicon , ESL handoff , C-to-Silicon Compiler , ESL , architect

Verification

Blogger of the Quarter Award -- Thanks!!!

Little did I know that when I accepted an innocent looking meeting propsal from my…

• 1 min read
funtional verification , Specman , e

Verification

New Blog series- Team ESL

Cadence is well known for its leadership in system verification leveraging its HW…

• 1 min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , embedded software , C-to-Silicon , ESL handoff , embedded SW engineer , Incisive Software Extensions , C-to-Silicon Compiler , ISX , Hardware/software co-verification , ESL

Verification

Exploring the Virtual Platform Part 4

Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read
microsoft , System Design and Verification , QEMU virtual platform , vista , ARM , wind river , monta

Verification

Post-Show Thoughts on DesignCon 2009

Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and…

• 1 min read
DesignCon , NXP , Functional Verification , coreuse , DVcon

Verification

Road Trip!

As at most companies these days, Cadence is doing what it can to minimize travel…

• 1 min read
Specman , Functional Verification , e , DVcon

System, PCB, & Package Design 

Focus Area: EDA Librarians - Manual Versus Automatic

Nope - I'm not talking about automobile transmissions ... I'll continue my series…

• 2 min read
SPB 16.2 , Library and design data management , APutomatic , PCB design , Librarians

Verification

Tech Pubs Tips Series Kickoff: Search for Single Character Words

[Team Specman welcomes the Technical Publications Team to our blog] Effectively documenting…

• 1 min read
Specman , C , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES

Analog/Custom Design

Your Virtuoso MMSIM Portfolio 2009 Performance Outlook

John Pierce, Product Marketing Director for Virtuoso Simulation application gives…

• 1 min read
mixed-signal simulators , Chip-level simulation , MMSIM , Virtuoso IC 6.1.3 , Block-level simulation , RF design , AMS simulation , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Constraint Construction: What's Its Function? Part 1 of 4

Have you found yourself frustrated at the lack of some decent timing constraints…

• 3 min read
Constraint Design , SoC-Encounter , Digital Implementation forums , SoC-Encounter 8.1 , 8.1 , Digital Implementation , Encounter Digital Implementation , Encounter Timing System , "SoC-Encounter"

SoC and IP

Memory's Recession: Actions and Realities

Now is the Winter of our Discontent: Five months into a memory industry recession…

• 7 min read

Digital Design

Programmatically Troubleshooting Timing Violations With "report_timing -collection…

Has something like the following ever happened to you? You've placed and optimized…

• 4 min read
Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

Digital Design

How to Create a Repeating Power Switch Pattern with addPowerSwitch

I mentioned in my last post that I'd been having lots of fun with power switches…

• 2 min read
Low Power , Digital Implementation , addpowerswitch
CDNS - Fix Layout Hompage