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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
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Blog - Post List

Latest blogs

Verification

Design space exploration

In his latest blog post Space Exploration ... design is , Grant Martin said that…

• 1 min read
high-level synthesis adoption , System Design and Verification , C-to-Silicon Compiler

Verification

Report from the CDV techtorials in SoCal

To follow-up on my previous post on the techtorials, I'm posting some photos from…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , coverage driven verification (CDV) , eRM

Verification

Flexibility Often Yields Unexpected Results

Often, when engineers set out to build something, the result is different from the…

• 4 min read
Functional Verification , Founders at Work Stories of Startups' Early Days , ISX (Incisive Software Extensions)

Verification

OVM is "Open" for Business

Open things are just curiosities until the ecosystem figures out how to turn them…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , Testbench simulation , OVM , OVMWorld

RF Engineering

Tip of the Week: Why Do Shooting and Harmonic Balance Phase Noise Results Differ…

Question: You are simulating your VCO in SpectreRF. You ran your PSS + Pnoise (noisetype…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Analog/Custom Design

Is mixed-signal simulation a fantasy?

The world is a mixed-signal one, or at least that's what were told. The concept of…

• less than a min read
mixed-signal simulators , Custom IC Design

Verification

Transaction-Based Acceleration - Second generation

Transaction-Based Acceleration is becoming more and more important as an extension…

• less than a min read
System Design and Verification

RF Engineering

Tip of the Week: Please explain in more practical (less theoretical) terms the concept…

Question: From spectre -h pnoise. I find the definition for oscillator linewidth…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

What's good about CheckSysConf? Plenty!

While I suspect that many of our customers have used or heard about the CheckSysConf…

• 3 min read
CheckSysConf , PCB design

Digital Design

Who Designed the iPhone?

When people ask you what you do for a living, is your response as clumsy as mine…

• 1 min read
Digital Implementation , iPhone

System, PCB, & Package Design 

Second Generation PCI Express spreading roots

According to Jag Bolaria of the Linley Group, the 5 Gbps version of PCI Express…

• less than a min read
PCB Signal and power integrity , SPB , SerDes , PCB design

Digital Design

Statistical Timing Analysis - Has its time arrived?

At 45nm chip designs, manufacturing and process control becomes increasingly difficult…

• 2 min read
Static timing analysis , STA , Digital Implementation , SSTA , corner analysis

Verification

Trip to SoCal "techtorials" on CDV

Just finished packing for a quick trip to Southern California to help kickoff a round…

• 1 min read
Functional Verification , Coverage-Driven Verification , CDV

Verification

Is anybody out there a Software Verification Engineer?

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I…

• 3 min read
co-verification engineer , System Design and Verification , EDA

System, PCB, & Package Design 

Did you know? Enriched schematic content available in PDF files from DEHDL (ConceptHDL…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various…

• 1 min read

RF Engineering

Measuring Transistor ft

So let’s consider a practical example of creating test benches and performing measurements…

• 5 min read
Measuring Transistor ft , RF design

System, PCB, & Package Design 

Shocking Technologies Becomes a Cadence Connections Member

In an announcement concurrent with Semicon West 2008, Shocking Technologies has …

• less than a min read
PCB Layout and routing , electrostatic discharge (ESD) dangers , Shocking Technologies , SPB , PCB design

Verification

C-to-Silicon Compiler Launch

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level…

• 1 min read
high-level synthesis adoption , C-to-Silicon Compiler

RF Engineering

Inductors On Demand, at least one RF design task can be really automated!

Inductors, transformers and transmission lines are critical components in any high…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso PCD , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design , Virtuoso Passive Component Designer , wireless integrated circuit verification
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