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Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
• 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

• 3 min read
hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

System, PCB, & Package Design 

BoardSurfers: Training Insights: Advanced Design Verification with RAVEL

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed…

• 5 min read
PCB , Allegro X PCB Editor , DRC , ravel , Allegro X Advanced Package Designer , APD , PCB Editor , Allegro Package Designer , PCB design , Constraints , allegro x

Computational Fluid Dynamics

Exploring Turbulence: An Introductory Approach

Key Points Turbulence is a widespread phenomenon that occurs across many scales…

• 5 min read
CFD , turbulence , LES

Digital Design

Semiconductors: Pioneering Extraordinary Growth in the 20th Century

Semiconductors have revolutionized the world, powering everything from smartphones…

• 3 min read
Static timing analysis , online courses , Cadence Online Support , RTL-to-GDSII , Joules , training bytes , Digital Implementation , Innovus , Synthesis , online training , physical implementation , cadence learning and support

SoC and IP

CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

Modern microelectronics is a new operating theater for many in the Defense Industrial…

• 2 min read
cadencelive , defense

Digital Design

Microlearning: The Snackable Knowledge Training Videos

Are you looking to level up your digital design skills—one byte at a time? Ohoo!…

• 5 min read
DFT , RTL2GDSII Flow , online courses , Functional Verification , Gate level simualtion , LEC , STA , Cadence training , training bytes , Digital Implementation , implementation , physical design , Synthesis , RTL design , RTL2GDSII Webinar

System, PCB, & Package Design 

System Analysis Knowledge Bytes - Optimizing LPDDR5X Performance with Sigrity X

This blog post explores the capabilities of Cadence Sigrity X Advanced SI in designing…

• 5 min read
Sigrity and Systems Analysis , TopXp , PBA , DDR interface , Sigrity X , system analysis , measurement , license , SPB , ddrx , lpddr5x , Sigrity , High Speed design , simulation , Advanced SI

SoC and IP

Time-of-Flight Decoding with Tensilica Vision DSPs

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be…

• 1 min read
IP , Consumer Electronics , cadence , video , Tensilica DSPs , ip cores , Tensilica , vision , semiconductor IP , cadencelive , imaging , image processing

Verification

eMMC: The Embedded Storage Powering On-Device AI

In today's world of increasingly intelligent devices, efficient and reliable storage…

• 2 min read
Verification IP , VIP , verification

Verification

Using PSS Registers with Perspec for Portable Programming Sequences

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus…

• 6 min read
Perspec , perspec system verifier , pss

Corporate News

Cadence to Power the Fourth Industrial Revolution in Collaboration with NVIDIA

The convergence of artificial intelligence (AI), robotics, and the internet of things…

• 1 min read
NVIDIA , Protium , Palladium , designed with cadence

SoC and IP

Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR ( LPDDR ) SDRAM has been one of the most widely used memories in the…

• 2 min read
Verification IP , Design IP , IP , VIP , JEDEC , LPDDR PHY IP , DRAM , LPDDR Controller IP , Design IP and Verification IP , Lpddr6

Analog/Custom Design

Custom Analog IP Migration in Virtuoso Studio

Join Cadence Training and presenters from our CIC experts for this free technical…

• 3 min read

System, PCB, & Package Design 

Efficient Automotive Electronic Component Design and Analysis

In the automotive industry, there is zero tolerance for field failures, as human…

• 3 min read

RF /マイクロ波設計

Cadence Microwave Office によるミックスモード・アウトフェージング増幅器の設計

近年の通信システムにおいて、基地局増幅器は高周波化・広帯域化が進み、高効率デバイスの開発が進められています。その中で負荷変調を用いた高効率化・広帯域化が注目されています…

• less than a min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , RF design , microwave office , japanese blog , scripting

Verification

NOP Flit Payload: A Dedicated Debug Channel

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols…

• 3 min read
NOP Flit Payload , debug , PCIe , PCIe 6.0 , PCI Express , Debug Chunk , NOP.Debug Flit Payload

Digital Design

Silicon Skylines: Crafting the Future of Electronics

The world of Electronic Design Automation (EDA) is fascinating, where we transform…

• 4 min read
electronic system design , Electronic Design Automation , training , training bytes , Semiconductor , online training

中文技术专区

Cadence 率先推出 eUSB2V2 IP 解决方案，助力打造高速连接新范式

为了提供更好的用户体验，包括高质量的视频传输、更新的笔记本电脑（例如最新的 AI PC）和其他前沿设备，都需要 5 纳米及以下的先进节点 SoC，以达成出色的功耗…

• less than a min read
eUSB2v2 , IP , TSMC , USB

Corporate News

NepTech – Tackling Marine Decarbonization with Fidelity CFD

Maritime transport is the backbone of international trade. It’s responsible for transporting…

• 2 min read
CFD , FINE Marine , designed with cadence , Fidelity CFD
CDNS - Fix Layout Hompage