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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview October 9th to 13th 2017

https://youtu.be/SVVE2vM4L6U Coming from Alum Rock Park (camera Carey Guo)…

• less than a min read
conformal , China , Chris Rowen , LEC , linley group , semi , grace hopper , vision

The India Circuit

IoT In Smart Factories, Healthcare, Agriculture and More

Last week’s blog ended with some of the IOT trends that Somshubhro Pal Choudhury…

• 4 min read
Automotive , IoT , smart factories , vertical markets , Internet of Things , robotics , ADAS , drones , healthcare , Smart Home

Breakfast Bytes

Scaling Embedded Inference Performance for Deep Learning

Tomorrow it is the Linley Microprocessor Conference and Pulin Desai of Cadence is…

• 6 min read
Vision P5 , deep learning , deeplearningmachinelearning , inference , convolutional neural network , training , Tensilica , CNN , neural network , Breakfast Bytes

Breakfast Bytes

AMD's Early Experience with Portable Stimulus

PSS is the Accellera Portable Stimulus Standard. Or I should say proposed standard…

• 4 min read
ryzen , AMD , Perspec , pss , portable stimulus , Breakfast Bytes

Learning and Support

Product Page: All Product-Related Information and Knowledge Content in One Place

In the past, some of you have expressed the desire to have all the information and…

• 1 min read
product , suppport , support resources

Verification

When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC…

As the stakes for winning server segment market share grow ever higher an increasing…

• 2 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Breakfast Bytes

Building a Business Model

You know how you sometimes say "the other day" as if it was last week, or maybe the…

• 8 min read
business model , pitch deck , garage ventures , reichert , Breakfast Bytes , venture capital

Breakfast Bytes

SJSU School of Cognitive Science

Jim Hogan is a graduate of San Jose State University. Despite the prestige of Stanford…

• 7 min read
san jose state university , san jose state , cognitive science , cognitive era , sjsu , Breakfast Bytes

The India Circuit

IOT: Are We There Yet?

One of the invited talks that we had at CDNLive was by Somshubhro Pal Choudhury,…

• 4 min read
hype cycle , CDNLive India , IoT , IOT stack , IOT trends , Internet of Things

Breakfast Bytes

Machine Learning for Higher Performance Machine Learning

The second day keynote at the recent (well, over a month ago, there's been lots to…

• 6 min read
tpu , Jeff Dean , google , hotchips , TensorFlow , machine learning , NAE goals , machinelearningdeeplearning , Tensor Processing Unit , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

• less than a min read
Whiteboard Wednesdays , machine learning , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 2nd to 6th 2017

https://youtu.be/uT2vXsXHV6s Coming from my car (camera Sean) Monday: AMD…

• less than a min read
deep learning , tensiilica , formal , EDPS , sjsu , portabe stimulus standard , Jim Hogan , pss , Formal verification

Verification

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

• 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation

Breakfast Bytes

SEMI Strategic Materials Conference

Yesterday I wrote about EDPS, which takes place at SEMI. Today, I'm writing about…

• 6 min read
China , semiconductor equipment , AMD , semi , moore's law , ARM , Breakfast Bytes

Learning and Support

Follow Video-Embedded Troubleshooting Articles for Easier Debugging

Finding a way out of situations is routine in today’s ever changing world—more so…

• 1 min read
COS , Self-Help , videos , Self Learning , what's new , Cadence Online Support , Support , troubleshooting , Cadence Support Portal , Cadence support

Breakfast Bytes

Solving the Design to Manufacturing Problems in Milpitas

HOT NEWS: In case you missed it, right at the end of last week, British GPU and CPU…

• 8 min read
Cisco , hvm , manufacturing , synopsys , data-centric computer architecture

Academic Network

EDA Summer Camp—Cadence Taiwan Hosts Top University Students

To help more students majoring in Electronics Engineering increase their understanding…

• 1 min read
Cadence Academic Network , academic workshop , academia , EDA

Verification

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

• 1 min read
Interconnect Workbench , customer feedback , success story , Palladium , Renesas

Analog/Custom Design

The Art of Analog Design: Part 3, Monte Carlo Sampling

In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider…

• 4 min read
Analog Design Environment , APS , ADE Explorer , Analog Simulation , analog , ADE , Monte Carlo , Analog Design Environment , ViVA , ADE Assembler , Cusstom IC Design
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