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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Suddenly You Are CEO. What Do You Do Next?

We've covered sales , marketing , and application engineering . Let's go up to the…

• 7 min read
board , chief executive officer , CEO

Breakfast Bytes

What's For Breakfast? Video Preview February 19th to 23rd 2018

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday…

• less than a min read
cookie , Spectre , Paul Kocher , CEO , Embedded World , 3rd party cookie

Breakfast Bytes

Zombies

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies…

• 8 min read
android , unix , iOS , zombie , linux , venture capital

Digital Design

Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose…

• 1 min read

Analog/Custom Design

Virtuoso Video Diary: Self-Paced Learning through Training Bytes

Cadence Education Services offers several online training courses and training bytes…

• 4 min read
training bytes , Virtuoso , Virtuoso Video Diary , Virtuoso Layout

Academic Network

3rd Tensilica Day in Hanover: Extending our Senses

Two events in a row are a coincidence, three events are a series. With these words…

• 2 min read
university , Hannover University , Cadence Academic Network , academic workshop , Tensilica

Breakfast Bytes

What Happens in a Patent Lawsuit?

One of the presentations in the exhibit hall, at the Chiphead Theater, was What Happens…

• 10 min read
expert witness , DesignCon , patent , lawyer , patent lawsuit

Whiteboard Wednesdays

Whiteboard Wednesdays - Can You Really Reduce DDR Power Dissipation by Reducing the…

In this week's Whiteboard Wednesday, Marc Greenberg examines the non-linear relationship…

• less than a min read
DDR Power , Whiteboard Wednesdays , Reduced Power DDR , Low Power DDR

The India Circuit

Rural India: Technology to the Rescue?

Last week I wrote about how mobile internet is expected to bring millions of Indians…

• 3 min read
3nethra , Forus Health , SBI Youth For India Fellowship , Rural India , Microsoft Mouse Mischief

Breakfast Bytes

9½ Years to Pluto, No Go-Arounds

Here's the scene. You are Alice Bowman, who in 2018 will give a keynote at DesignCon…

• 7 min read
pluto , mu69 , DesignCon , new horizons

SoC and IP

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

• 1 min read
DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging

Breakfast Bytes

Advanced Packaging Needs Advanced Tools

At the recent DesignCon, Cadence's John Park presented Advanced Packaging Trends…

• 5 min read
vsdp , virtuoso system design platform , Virtuoso , OrbitIO , more than Moore , 3D packaging

SoC and IP

What I Learned About System Design Enablement at DesignCon

While attending the recent DesignCon show for the first time, I was struck by the…

• 2 min read
IP , IP integration , SDE , Sigrity , system design enablement

SoC and IP

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

• 2 min read
IP , IP integration , SDE , noise , Sigrity

Breakfast Bytes

Application Engineers Are Like Gold

I wrote recently about my experiences Running a Salesforce , and one of the key aspects…

• 4 min read
application engineers

Analog/Custom Design

Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing

In order to drive high current and to minimize routing resistivity, it is desirable…

• 3 min read
interactive coloring , stranded wire , Virtuoso Space-based Router , weStrandedColorMode , leHiCreateStrandedWire , blockage avoidance , weStrandedAlignCollinearMode , Virtuoso , Stranded Wire Context-sensitive Menu , Virtuoso Video Diary , tieout , weStrandSpacing , tapering in stranded wire , Custom IC Design , WSP support in Stranded Wire , space based router , Custom IC , weStrandedLadderAtTurn , weStrandNum

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (6 of 8)

Simulating with IBIS-AMI Models By this point in the process, the SerDes component…

• 3 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Warsaw to Canary Islands to Madrid to Staten Island to California: Michal's Jour…

Some people grow up in the US, go to high school, get into a good engineering or…

• 8 min read
logical equivalence checking , LEC , Stanford , verplex , Berkeley , Poland , Formal verification

Breakfast Bytes

What's For Breakfast? Video Preview February 12th to 16th 2018

https://youtu.be/wwioFa3JGuc Coming from the Cadence basketball court (camera…

• less than a min read
PCB , pluto , packaging , patent , more than Moore , PCB design , zombie , CEO
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